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Commit f363c407 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nicolas Ferre
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ARM: at91: make sdram/ddr register base soc independent 



Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 1a269ade

arch/arm/mach-at91/at91rm9200.c

+1 −0
Original line number Diff line number Diff line
@@ -320,6 +320,7 @@ static void __init at91rm9200_map_io(void) 
static void __init at91rm9200_ioremap_registers(void)

{

	at91rm9200_ioremap_st(AT91RM9200_BASE_ST);

	at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);

}



static void __init at91rm9200_initialize(void)

arch/arm/mach-at91/at91rm9200_devices.c

+7 −6
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <mach/board.h>

#include <mach/at91rm9200.h>

#include <mach/at91rm9200_mc.h>

#include <mach/at91_ramc.h>



#include "generic.h"
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data) 
	data->chipselect = 4;		/* can only use EBI ChipSelect 4 */



	/* CF takes over CS4, CS5, CS6 */

	csa = at91_sys_read(AT91_EBI_CSA);

	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);

	csa = at91_ramc_read(0, AT91_EBI_CSA);

	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);



	/*

	 * Static memory controller timing adjustments.

	 * REVISIT:  these timings are in terms of MCK cycles, so

	 * when MCK changes (cpufreq etc) so must these values...

	 */

	at91_sys_write(AT91_SMC_CSR(4),

	at91_ramc_write(0, AT91_SMC_CSR(4),

				  AT91_SMC_ACSS_STD

				| AT91_SMC_DBW_16

				| AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) 
		return;



	/* enable the address range of CS3 */

	csa = at91_sys_read(AT91_EBI_CSA);

	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	csa = at91_ramc_read(0, AT91_EBI_CSA);

	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);



	/* set the bus interface characteristics */

	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN

	at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN

		| AT91_SMC_NWS_(5)

		| AT91_SMC_TDF_(1)

		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */

arch/arm/mach-at91/at91sam9260.c

+1 −0
Original line number Diff line number Diff line
@@ -325,6 +325,7 @@ static void __init at91sam9260_ioremap_registers(void) 
{

	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);

	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);

	at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);

	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);

	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);

	at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);

arch/arm/mach-at91/at91sam9261.c

+1 −0
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ static void __init at91sam9261_ioremap_registers(void) 
{

	at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);

	at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);

	at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);

	at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);

	at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);

	at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);

arch/arm/mach-at91/at91sam9263.c

+2 −0
Original line number Diff line number Diff line
@@ -303,6 +303,8 @@ static void __init at91sam9263_ioremap_registers(void) 
{

	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);

	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);

	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);

	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);

	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);

	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);

	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);