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Commit f2e442fd authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines 



This patch gets rid of all CONFIG_SOC_AU1XXX defines in
DMA/DBDMA-related code.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2704/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d4f07ae7

arch/mips/alchemy/common/dbdma.c

+91 −112
Original line number Diff line number Diff line
@@ -40,8 +40,6 @@ 
#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/au1xxx_dbdma.h>



#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)



/*

 * The Descriptor Based DMA supports up to 16 channels.

 *
@@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr = 
			(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);

static int dbdma_initialized;



static dbdev_tab_t dbdev_tab[] = {

#ifdef CONFIG_SOC_AU1550

static dbdev_tab_t *dbdev_tab;



static dbdev_tab_t au1550_dbdev_tab[] __initdata = {

	/* UARTS */

	{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

	{ DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },

	{ DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },

	{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },

	{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },

	{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8, 0x11400000, 0, 0 },



	/* EXT DMA */

	{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },



	/* USB DEV */

	{ DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },

	{ DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },

	{ DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },

	{ DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },



	/* PSC 0 */

	{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },



	/* PSC 1 */

	{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },



	/* PSC 2 */

	{ DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },

	{ DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },



	/* PSC 3 */

	{ DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },

	{ DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },



	{ DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 },	/* PCI */

	{ DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 },	/* NAND */

	{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN,  4, 8, 0x10200000, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN,  4, 8, 0x10200010, 0, 0 },

	{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN,  4, 8, 0x10200014, 0, 0 },



	/* PSCs */

	{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,  0, 0, 0x11a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,  0, 0, 0x11b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,  0, 0, 0x10a0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },

	{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,  0, 0, 0x10b0001c, 0, 0 },



	{ AU1550_DSCR_CMD0_PCI_WRITE,  0, 0, 0, 0x00000000, 0, 0 },  /* PCI */

	{ AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */



	/* MAC 0 */

	{ DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



	/* MAC 1 */

	{ DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



#endif /* CONFIG_SOC_AU1550 */

	{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },

	{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },



#ifdef CONFIG_SOC_AU1200

	{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },

	{ DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },

	{ DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },



	{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

};



	{ DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

static dbdev_tab_t au1200_dbdev_tab[] __initdata = {

	{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },

	{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },

	{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },

	{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8, 0x11200000, 0, 0 },



	{ DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

	{ DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },

	{ DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },

	{ DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },

	{ AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

	{ DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },

	{ DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8, 0x10600004, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },

	{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  4, 8, 0x10680004, 0, 0 },



	{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },

	{ DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },

	{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },



	{ DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },

	{ DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },

	{ DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },

	{ DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_TX,   DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_RX,   DEV_FLAGS_IN,  0, 16, 0x11a0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_TX,   DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_RX,   DEV_FLAGS_IN,  0, 16, 0x11b0001c, 0, 0 },

	{ AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXA,  DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXB,  DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_RXC,  DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },

	{ AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



#endif /* CONFIG_SOC_AU1200 */

	{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },



	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },

	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },



	/* Provide 16 user definable device types */

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

	{ ~0, 0, 0, 0, 0, 0, 0 },

};



#define DBDEV_TAB_SIZE	ARRAY_SIZE(dbdev_tab)



/* 32 predefined plus 32 custom */

#define DBDEV_TAB_SIZE		64



static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
@@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = { 
	.resume		= alchemy_dbdma_resume,

};



static int __init au1xxx_dbdma_init(void)

static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)

{

	int irq_nr, ret;

	int ret;



	dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);

	if (!dbdev_tab)

		return -ENOMEM;



	memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));

	for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)

		dbdev_tab[ret].dev_id = ~0;



	dbdma_gptr->ddma_config = 0;

	dbdma_gptr->ddma_throttle = 0;

	dbdma_gptr->ddma_inten = 0xffff;

	au_sync();



	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1550:

		irq_nr = AU1550_DDMA_INT;

		break;

	case ALCHEMY_CPU_AU1200:

		irq_nr = AU1200_DDMA_INT;

		break;

	default:

		return -ENODEV;

	}



	ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,

			"Au1xxx dbdma", (void *)dbdma_gptr);

	ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",

			  (void *)dbdma_gptr);

	if (ret)

		printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");

	else {

		dbdma_initialized = 1;

		printk(KERN_INFO "Alchemy DBDMA initialized\n");

		register_syscore_ops(&alchemy_dbdma_syscore_ops);

	}



	return ret;

}

subsys_initcall(au1xxx_dbdma_init);



#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
 
static int __init alchemy_dbdma_init(void)

{

	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1550:

		return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);

	case ALCHEMY_CPU_AU1200:

		return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);

	}

	return 0;

}

subsys_initcall(alchemy_dbdma_init);

arch/mips/alchemy/common/dma.c

+28 −32
Original line number Diff line number Diff line
@@ -40,8 +40,6 @@ 
#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/au1000_dma.h>



#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \

    defined(CONFIG_SOC_AU1100)

/*

 * A note on resource allocation:

 *
@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str, 
	const struct dma_dev *dev;

	int i, ret;



#if defined(CONFIG_SOC_AU1100)

	if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {

		if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))

			return -EINVAL;

#else

	} else {

		if (dev_id < 0 || dev_id >= DMA_NUM_DEV)

			return -EINVAL;

#endif

	}



	for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)

		if (au1000_dma_table[i].dev_id < 0)
@@ -264,5 +262,3 @@ static int __init au1000_dma_init(void) 
	return 0;

}

arch_initcall(au1000_dma_init);
 


#endif /* AU1000 AU1500 AU1100 */

arch/mips/alchemy/common/platform.c

+8 −8
Original line number Diff line number Diff line
@@ -263,13 +263,13 @@ static struct resource au1200_mmc0_resources[] = { 
		.flags		= IORESOURCE_IRQ,

	},

	[2] = {

		.start		= DSCR_CMD0_SDMS_TX0,

		.end		= DSCR_CMD0_SDMS_TX0,

		.start		= AU1200_DSCR_CMD0_SDMS_TX0,

		.end		= AU1200_DSCR_CMD0_SDMS_TX0,

		.flags		= IORESOURCE_DMA,

	},

	[3] = {

		.start          = DSCR_CMD0_SDMS_RX0,

		.end		= DSCR_CMD0_SDMS_RX0,

		.start          = AU1200_DSCR_CMD0_SDMS_RX0,

		.end		= AU1200_DSCR_CMD0_SDMS_RX0,

		.flags          = IORESOURCE_DMA,

	}

};
@@ -299,13 +299,13 @@ static struct resource au1200_mmc1_resources[] = { 
		.flags		= IORESOURCE_IRQ,

	},

	[2] = {

		.start		= DSCR_CMD0_SDMS_TX1,

		.end		= DSCR_CMD0_SDMS_TX1,

		.start		= AU1200_DSCR_CMD0_SDMS_TX1,

		.end		= AU1200_DSCR_CMD0_SDMS_TX1,

		.flags		= IORESOURCE_DMA,

	},

	[3] = {

		.start          = DSCR_CMD0_SDMS_RX1,

		.end		= DSCR_CMD0_SDMS_RX1,

		.start          = AU1200_DSCR_CMD0_SDMS_RX1,

		.end		= AU1200_DSCR_CMD0_SDMS_RX1,

		.flags          = IORESOURCE_DMA,

	}

};

arch/mips/alchemy/devboards/db1200/platform.c

+10 −10
Original line number Diff line number Diff line
@@ -215,8 +215,8 @@ static struct resource db1200_ide_res[] = { 
		.flags	= IORESOURCE_IRQ,

	},

	[2] = {

		.start	= DSCR_CMD0_DMA_REQ1,

		.end	= DSCR_CMD0_DMA_REQ1,

		.start	= AU1200_DSCR_CMD0_DMA_REQ1,

		.end	= AU1200_DSCR_CMD0_DMA_REQ1,

		.flags	= IORESOURCE_DMA,

	},

};
@@ -358,13 +358,13 @@ static struct resource au1200_psc0_res[] = { 
		.flags	= IORESOURCE_IRQ,

	},

	[2] = {

		.start	= DSCR_CMD0_PSC0_TX,

		.end	= DSCR_CMD0_PSC0_TX,

		.start	= AU1200_DSCR_CMD0_PSC0_TX,

		.end	= AU1200_DSCR_CMD0_PSC0_TX,

		.flags	= IORESOURCE_DMA,

	},

	[3] = {

		.start	= DSCR_CMD0_PSC0_RX,

		.end	= DSCR_CMD0_PSC0_RX,

		.start	= AU1200_DSCR_CMD0_PSC0_RX,

		.end	= AU1200_DSCR_CMD0_PSC0_RX,

		.flags	= IORESOURCE_DMA,

	},

};
@@ -416,13 +416,13 @@ static struct resource au1200_psc1_res[] = { 
		.flags	= IORESOURCE_IRQ,

	},

	[2] = {

		.start	= DSCR_CMD0_PSC1_TX,

		.end	= DSCR_CMD0_PSC1_TX,

		.start	= AU1200_DSCR_CMD0_PSC1_TX,

		.end	= AU1200_DSCR_CMD0_PSC1_TX,

		.flags	= IORESOURCE_DMA,

	},

	[3] = {

		.start	= DSCR_CMD0_PSC1_RX,

		.end	= DSCR_CMD0_PSC1_RX,

		.start	= AU1200_DSCR_CMD0_PSC1_RX,

		.end	= AU1200_DSCR_CMD0_PSC1_RX,

		.flags	= IORESOURCE_DMA,

	},

};

arch/mips/alchemy/devboards/pb1200/platform.c

+2 −2
Original line number Diff line number Diff line
@@ -118,8 +118,8 @@ static struct resource ide_resources[] = { 
		.flags	= IORESOURCE_IRQ

	},

	[2] = {

		.start	= DSCR_CMD0_DMA_REQ1,

		.end	= DSCR_CMD0_DMA_REQ1,

		.start	= AU1200_DSCR_CMD0_DMA_REQ1,

		.end	= AU1200_DSCR_CMD0_DMA_REQ1,

		.flags	= IORESOURCE_DMA,

	},

};