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Commit f2a68272 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Quit using undefined behavior of ADDU in 64-bit atomic operations. 



For 64-bit, we must use DADDU and DSUBU.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1483/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 31c984a5

arch/mips/include/asm/atomic.h

+12 −12
Original line number Diff line number Diff line
@@ -434,7 +434,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%0, %1		# atomic64_add		\n"

		"	addu	%0, %2					\n"

		"	daddu	%0, %2					\n"

		"	scd	%0, %1					\n"

		"	beqzl	%0, 1b					\n"

		"	.set	mips0					\n"
@@ -446,7 +446,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%0, %1		# atomic64_add		\n"

		"	addu	%0, %2					\n"

		"	daddu	%0, %2					\n"

		"	scd	%0, %1					\n"

		"	beqz	%0, 2f					\n"

		"	.subsection 2					\n"
@@ -479,7 +479,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%0, %1		# atomic64_sub		\n"

		"	subu	%0, %2					\n"

		"	dsubu	%0, %2					\n"

		"	scd	%0, %1					\n"

		"	beqzl	%0, 1b					\n"

		"	.set	mips0					\n"
@@ -491,7 +491,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%0, %1		# atomic64_sub		\n"

		"	subu	%0, %2					\n"

		"	dsubu	%0, %2					\n"

		"	scd	%0, %1					\n"

		"	beqz	%0, 2f					\n"

		"	.subsection 2					\n"
@@ -524,10 +524,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%1, %2		# atomic64_add_return	\n"

		"	addu	%0, %1, %3				\n"

		"	daddu	%0, %1, %3				\n"

		"	scd	%0, %2					\n"

		"	beqzl	%0, 1b					\n"

		"	addu	%0, %1, %3				\n"

		"	daddu	%0, %1, %3				\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter)
@@ -538,10 +538,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%1, %2		# atomic64_add_return	\n"

		"	addu	%0, %1, %3				\n"

		"	daddu	%0, %1, %3				\n"

		"	scd	%0, %2					\n"

		"	beqz	%0, 2f					\n"

		"	addu	%0, %1, %3				\n"

		"	daddu	%0, %1, %3				\n"

		"	.subsection 2					\n"

		"2:	b	1b					\n"

		"	.previous					\n"
@@ -576,10 +576,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%1, %2		# atomic64_sub_return	\n"

		"	subu	%0, %1, %3				\n"

		"	dsubu	%0, %1, %3				\n"

		"	scd	%0, %2					\n"

		"	beqzl	%0, 1b					\n"

		"	subu	%0, %1, %3				\n"

		"	dsubu	%0, %1, %3				\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp), "=m" (v->counter)

		: "Ir" (i), "m" (v->counter)
@@ -590,10 +590,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 
		__asm__ __volatile__(

		"	.set	mips3					\n"

		"1:	lld	%1, %2		# atomic64_sub_return	\n"

		"	subu	%0, %1, %3				\n"

		"	dsubu	%0, %1, %3				\n"

		"	scd	%0, %2					\n"

		"	beqz	%0, 2f					\n"

		"	subu	%0, %1, %3				\n"

		"	dsubu	%0, %1, %3				\n"

		"	.subsection 2					\n"

		"2:	b	1b					\n"

		"	.previous					\n"