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Commit f2626ba9 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-fixes' into clk-next 

* clk-fixes:
  clk: tegra: super: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warning for pll_m
  clk: tegra: Use definition for pll_u override bit
  clk: tegra: Fix warning caused by pll_u failing to lock
  clk: tegra: Fix clock sources for Tegra210 EMC
  clk: tegra: Add the APB2APE audio clock on Tegra210
  clk: tegra: Add missing of_node_put()
  clk: tegra: Fix PLLE SS coefficients
  clk: tegra: Fix typos around clearing PLLE bits during enable
  clk: tegra: Do not disable PLLE when under hardware control
  clk: tegra: Fix pllx dyn step calculation
  clk: tegra: pll: Fix potential sleeping-while-atomic
  clk: tegra: Fix the misnaming of nvenc from msenc
  clk: tegra: Fix naming of MISC registers
  clk: tegra: Remove improper flags for lock_enable
  clk: tegra: Fix divider on VI_I2C
parents 1e42754e 0e954fea

drivers/clk/tegra/clk-emc.c

+4 −2
Original line number Diff line number Diff line
@@ -450,8 +450,10 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra, 
		struct emc_timing *timing = tegra->timings + (i++);



		err = load_one_timing_from_dt(tegra, timing, child);

		if (err)

		if (err) {

			of_node_put(child);

			return err;

		}



		timing->ram_code = ram_code;

	}
@@ -499,9 +501,9 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 
		 * fuses until the apbmisc driver is loaded.

		 */

		err = load_timings_from_dt(tegra, node, node_ram_code);

		of_node_put(node);

		if (err)

			return ERR_PTR(err);

		of_node_put(node);

		break;

	}

drivers/clk/tegra/clk-id.h

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ enum clk_id { 
	tegra_clk_afi,

	tegra_clk_amx,

	tegra_clk_amx1,

	tegra_clk_apb2ape,

	tegra_clk_apbdma,

	tegra_clk_apbif,

	tegra_clk_ape,

drivers/clk/tegra/clk-pll.c

+32 −18
Original line number Diff line number Diff line
@@ -86,15 +86,21 @@ 
#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\

				PLLE_SS_CNTL_SSC_BYP)

#define PLLE_SS_MAX_MASK 0x1ff

#define PLLE_SS_MAX_VAL 0x25

#define PLLE_SS_MAX_VAL_TEGRA114 0x25

#define PLLE_SS_MAX_VAL_TEGRA210 0x21

#define PLLE_SS_INC_MASK (0xff << 16)

#define PLLE_SS_INC_VAL (0x1 << 16)

#define PLLE_SS_INCINTRV_MASK (0x3f << 24)

#define PLLE_SS_INCINTRV_VAL (0x20 << 24)

#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)

#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)

#define PLLE_SS_COEFFICIENTS_MASK \

	(PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)

#define PLLE_SS_COEFFICIENTS_VAL \

	(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)

#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \

	(PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\

	 PLLE_SS_INCINTRV_VAL_TEGRA114)

#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \

	(PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\

	 PLLE_SS_INCINTRV_VAL_TEGRA210)



#define PLLE_AUX_PLLP_SEL	BIT(2)

#define PLLE_AUX_USE_LOCKDET	BIT(3)
@@ -880,7 +886,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) 
static int clk_plle_enable(struct clk_hw *hw)

{

	struct tegra_clk_pll *pll = to_clk_pll(hw);

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));

	struct tegra_clk_pll_freq_table sel;

	u32 val;

	int err;
@@ -1378,7 +1384,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	u32 val;

	int ret;

	unsigned long flags = 0;

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));



	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

		return -EINVAL;
@@ -1401,7 +1407,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val |= PLLE_MISC_IDDQ_SW_CTRL;

	val &= ~PLLE_MISC_IDDQ_SW_VALUE;

	val |= PLLE_MISC_PLLE_PTS;

	val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;

	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);

	pll_writel_misc(val, pll);

	udelay(5);
@@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val = pll_readl(PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);

	val &= ~PLLE_SS_COEFFICIENTS_MASK;

	val |= PLLE_SS_COEFFICIENTS_VAL;

	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;

	pll_writel(val, PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);

	pll_writel(val, PLLE_SS_CTRL, pll);
@@ -2012,9 +2018,9 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	struct tegra_clk_pll *pll = to_clk_pll(hw);

	struct tegra_clk_pll_freq_table sel;

	u32 val;

	int ret;

	int ret = 0;

	unsigned long flags = 0;

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));



	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

		return -EINVAL;
@@ -2022,22 +2028,20 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	if (pll->lock)

		spin_lock_irqsave(pll->lock, flags);



	val = pll_readl(pll->params->aux_reg, pll);

	if (val & PLLE_AUX_SEQ_ENABLE)

		goto out;



	val = pll_readl_base(pll);

	val &= ~BIT(30); /* Disable lock override */

	pll_writel_base(val, pll);



	val = pll_readl(pll->params->aux_reg, pll);

	val |= PLLE_AUX_ENABLE_SWCTL;

	val &= ~PLLE_AUX_SEQ_ENABLE;

	pll_writel(val, pll->params->aux_reg, pll);

	udelay(1);



	val = pll_readl_misc(pll);

	val |= PLLE_MISC_LOCK_ENABLE;

	val |= PLLE_MISC_IDDQ_SW_CTRL;

	val &= ~PLLE_MISC_IDDQ_SW_VALUE;

	val |= PLLE_MISC_PLLE_PTS;

	val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;

	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);

	pll_writel_misc(val, pll);

	udelay(5);
@@ -2067,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	val = pll_readl(PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);

	val &= ~PLLE_SS_COEFFICIENTS_MASK;

	val |= PLLE_SS_COEFFICIENTS_VAL;

	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;

	pll_writel(val, PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);

	pll_writel(val, PLLE_SS_CTRL, pll);
@@ -2104,15 +2108,25 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw) 
	if (pll->lock)

		spin_lock_irqsave(pll->lock, flags);



	/* If PLLE HW sequencer is enabled, SW should not disable PLLE */

	val = pll_readl(pll->params->aux_reg, pll);

	if (val & PLLE_AUX_SEQ_ENABLE)

		goto out;



	val = pll_readl_base(pll);

	val &= ~PLLE_BASE_ENABLE;

	pll_writel_base(val, pll);



	val = pll_readl(pll->params->aux_reg, pll);

	val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;

	pll_writel(val, pll->params->aux_reg, pll);



	val = pll_readl_misc(pll);

	val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;

	pll_writel_misc(val, pll);

	udelay(1);



out:

	if (pll->lock)

		spin_unlock_irqrestore(pll->lock, flags);

}

drivers/clk/tegra/clk-tegra-periph.c

+3 −2
Original line number Diff line number Diff line
@@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = { 
	XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),

	XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),

	MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),

	MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),

	MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),

	MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),

	MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),

	MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
@@ -782,7 +782,7 @@ static struct tegra_periph_init_data periph_clks[] = { 
	NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),

	MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),

	MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),

	MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),

	I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),

	MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),

	MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),

	MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
@@ -829,6 +829,7 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),

	GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),

	GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),

	GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),

};



static struct tegra_periph_init_data div_clks[] = {

drivers/clk/tegra/clk-tegra-super-gen4.c

+3 −3
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 
					 "pll_p", "pll_p_out4", "unused",

					 "unused", "pll_x", "pll_x_out0" };



const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {

static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {

	.gen = gen4,

	.sclk_parents = sclk_parents,

	.cclk_g_parents = cclk_g_parents,
@@ -93,7 +93,7 @@ static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unu 
					"unused", "unused", "unused", "unused",

					"dfllCPU_out" };



const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {

static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {

	.gen = gen5,

	.sclk_parents = sclk_parents_gen5,

	.cclk_g_parents = cclk_g_parents_gen5,
@@ -171,7 +171,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
	*dt_clk = clk;

}



void __init tegra_super_clk_init(void __iomem *clk_base,

static void __init tegra_super_clk_init(void __iomem *clk_base,

				void __iomem *pmc_base,

				struct tegra_clk *tegra_clks,

				struct tegra_clk_pll_params *params,