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Commit f2335330 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: clean up and simplify i9xx_crtc_mode_set wrt PLL handling 



Flat out skip anything to do with PLL if we have a DSI encoder (and thus
DSI PLL). Also skip PLL computation if the encoder has already set
clocks. This allows for some tidying up of the code, including a
superfluous call to intel_limit() for LVDS downclock path.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 46a3f4a3

drivers/gpu/drm/i915/intel_display.c

+22 −22
Original line number Diff line number Diff line
@@ -4918,9 +4918,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		num_connectors++;

	}



	if (is_dsi)

		goto skip_dpll;



	if (!intel_crtc->config.clock_set) {

		refclk = i9xx_get_refclk(crtc, num_connectors);



	if (!is_dsi && !intel_crtc->config.clock_set) {

		/*

		 * Returns a set of divisors for the desired target clock with

		 * the given refclk, or FALSE.  The returned values represent
@@ -4931,20 +4934,18 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		ok = dev_priv->display.find_dpll(limit, crtc,

						 intel_crtc->config.port_clock,

						 refclk, NULL, &clock);

		if (!ok && !intel_crtc->config.clock_set) {

		if (!ok) {

			DRM_ERROR("Couldn't find PLL settings for mode!\n");

			return -EINVAL;

		}

	}



		if (is_lvds && dev_priv->lvds_downclock_avail) {

			/*

		 * Ensure we match the reduced clock's P to the target clock.

		 * If the clocks don't match, we can't switch the display clock

		 * by using the FP0/FP1. In such case we will disable the LVDS

		 * downclock feature.

			 * Ensure we match the reduced clock's P to the target

			 * clock.  If the clocks don't match, we can't switch

			 * the display clock by using the FP0/FP1. In such case

			 * we will disable the LVDS downclock feature.

			 */

		limit = intel_limit(crtc, refclk);

			has_reduced_clock =

				dev_priv->display.find_dpll(limit, crtc,

							    dev_priv->lvds_downclock,
@@ -4952,7 +4953,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
							    &reduced_clock);

		}

		/* Compat-code for transition, will disappear. */

	if (!intel_crtc->config.clock_set) {

		intel_crtc->config.dpll.n = clock.n;

		intel_crtc->config.dpll.m1 = clock.m1;

		intel_crtc->config.dpll.m2 = clock.m2;
@@ -4965,7 +4965,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
				has_reduced_clock ? &reduced_clock : NULL,

				num_connectors);

	} else if (IS_VALLEYVIEW(dev)) {

		if (!is_dsi)

		vlv_update_pll(intel_crtc);

	} else {

		i9xx_update_pll(intel_crtc,
@@ -4973,6 +4972,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
                                num_connectors);

	}



skip_dpll:

	/* Set up the display plane register */

	dspcntr = DISPPLANE_GAMMA_ENABLE;