Commit f1f5e414 authored Jul 24, 2015 by Alex Smith Committed by Ralf Baechle Sep 03, 2015

MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms



The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.

Signed-off-by: Alex Smith <alex.smith@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10769/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 8c172467

arch/mips/include/asm/pgtable-bits.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
		#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
		#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */

		#elif defined(CONFIG_MACH_JZ4740)
		#elif defined(CONFIG_MACH_INGENIC)

		/* Ingenic uses the WA bit to achieve write-combine memory writes */
		#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)