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Commit f1d6e31d authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v3.10/fixes-v3.10-rc4' of... 

Merge tag 'omap-for-v3.10/fixes-v3.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

From Tony Lindgren, a set of small fixes for omaps for the -rc cycle:

- am7303 iva2 reset PM regression fix
- am33xx uart2 dma channel fix
- am33xx gpmc properties fix
- omap44xx rtc wake-up mux fix for nirq pins
- omap36xx clock divider restore fix

There's also one tiny non-critical .dts fix for omap5
timer pwm properties.

* tag 'omap-for-v3.10/fixes-v3.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: omap3: clock: fix wrong container_of in clock36xx.c
  ARM: dts: OMAP5: Fix missing PWM capability to timer nodes
  ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line
  ARM: dts: AM33xx: Fix properties on gpmc node
  arm: omap2: fix AM33xx hwmod infos for UART2
  ARM: OMAP3: Fix iva2_pwrdm settings for 3703
parents 090878aa 03c0d271

arch/arm/boot/dts/am33xx.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -409,8 +409,8 @@ 
			ti,hwmods = "gpmc";

			reg = <0x50000000 0x2000>;

			interrupts = <100>;

			num-cs = <7>;

			num-waitpins = <2>;

			gpmc,num-cs = <7>;

			gpmc,num-waitpins = <2>;

			#address-cells = <2>;

			#size-cells = <1>;

			status = "disabled";

arch/arm/boot/dts/omap4-panda-common.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -56,9 +56,23 @@ 
	};

};



&omap4_pmx_wkup {

	pinctrl-names = "default";

	pinctrl-0 = <

			&twl6030_wkup_pins

	>;



	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {

		pinctrl-single,pins = <

			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */

		>;

	};

};



&omap4_pmx_core {

	pinctrl-names = "default";

	pinctrl-0 = <

			&twl6030_pins

			&twl6040_pins

			&mcpdm_pins

			&mcbsp1_pins
@@ -66,6 +80,12 @@ 
			&tpd12s015_pins

	>;



	twl6030_pins: pinmux_twl6030_pins {

		pinctrl-single,pins = <

			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */

		>;

	};



	twl6040_pins: pinmux_twl6040_pins {

		pinctrl-single,pins = <

			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */

arch/arm/boot/dts/omap4-sdp.dts

+20 −0
Original line number Diff line number Diff line
@@ -142,9 +142,23 @@ 
	};

};



&omap4_pmx_wkup {

	pinctrl-names = "default";

	pinctrl-0 = <

			&twl6030_wkup_pins

	>;



	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {

		pinctrl-single,pins = <

			0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */

		>;

	};

};



&omap4_pmx_core {

	pinctrl-names = "default";

	pinctrl-0 = <

			&twl6030_pins

			&twl6040_pins

			&mcpdm_pins

			&dmic_pins
@@ -179,6 +193,12 @@ 
		>;

	};



	twl6030_pins: pinmux_twl6030_pins {

		pinctrl-single,pins = <

			0x15e 0x4118	/* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */

		>;

	};



	twl6040_pins: pinmux_twl6040_pins {

		pinctrl-single,pins = <

			0xe0 0x3	/* hdq_sio.gpio_127 OUTPUT | MODE3 */

arch/arm/boot/dts/omap5.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -538,6 +538,7 @@ 
			interrupts = <0 41 0x4>;

			ti,hwmods = "timer5";

			ti,timer-dsp;

			ti,timer-pwm;

		};



		timer6: timer@4013a000 {
@@ -574,6 +575,7 @@ 
			reg = <0x4803e000 0x80>;

			interrupts = <0 45 0x4>;

			ti,hwmods = "timer9";

			ti,timer-pwm;

		};



		timer10: timer@48086000 {
@@ -581,6 +583,7 @@ 
			reg = <0x48086000 0x80>;

			interrupts = <0 46 0x4>;

			ti,hwmods = "timer10";

			ti,timer-pwm;

		};



		timer11: timer@48088000 {

arch/arm/mach-omap2/clock36xx.c

+9 −9
Original line number Diff line number Diff line
@@ -20,11 +20,12 @@ 


#include <linux/kernel.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/io.h>



#include "clock.h"

#include "clock36xx.h"



#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)



/**

 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@ 
 */

int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)

{

	struct clk_hw_omap *parent;

	struct clk_divider *parent;

	struct clk_hw *parent_hw;

	u32 dummy_v, orig_v, clksel_shift;

	u32 dummy_v, orig_v;

	int ret;



	/* Clear PWRDN bit of HSDIVIDER */

	ret = omap2_dflt_clk_enable(clk);



	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));

	parent = to_clk_hw_omap(parent_hw);

	parent = to_clk_divider(parent_hw);



	/* Restore the dividers */

	if (!ret) {

		clksel_shift = __ffs(parent->clksel_mask);

		orig_v = __raw_readl(parent->clksel_reg);

		orig_v = __raw_readl(parent->reg);

		dummy_v = orig_v;



		/* Write any other value different from the Read value */

		dummy_v ^= (1 << clksel_shift);

		__raw_writel(dummy_v, parent->clksel_reg);

		dummy_v ^= (1 << parent->shift);

		__raw_writel(dummy_v, parent->reg);



		/* Write the original divider */

		__raw_writel(orig_v, parent->clksel_reg);

		__raw_writel(orig_v, parent->reg);

	}



	return ret;