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Commit f19baaea authored by Brice Goglin's avatar Brice Goglin Committed by Jeff Garzik
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myri10ge: more Intel chipsets providing aligned PCIe completions 



Add the Intel 5000 southbridge (aka Intel 6310/6311/6321ESB) PCIe ports
and the Intel E30x0 chipsets to the whitelist of aligned PCIe completion.

Signed-off-by: default avatarBrice Goglin <brice@myri.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent ae8509b1

drivers/net/myri10ge/myri10ge.c

+16 −0
Original line number Diff line number Diff line
@@ -2487,6 +2487,10 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp) 


#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7

#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa

#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510

#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b

#define PCI_DEVICE_ID_INTEL_E3000_PCIE	0x2779

#define PCI_DEVICE_ID_INTEL_E3010_PCIE	0x277a

#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140

#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
@@ -2526,6 +2530,18 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp) 
				PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST

				&& bridge->device <=

				PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)

			    /* All Intel E3000/E3010 PCIE ports */

			    || (bridge->vendor == PCI_VENDOR_ID_INTEL

				&& (bridge->device ==

				    PCI_DEVICE_ID_INTEL_E3000_PCIE

				    || bridge->device ==

				    PCI_DEVICE_ID_INTEL_E3010_PCIE))

			    /* All Intel 6310/6311/6321ESB PCIE ports */

			    || (bridge->vendor == PCI_VENDOR_ID_INTEL

				&& bridge->device >=

				PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1

				&& bridge->device <=

				PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)

			    /* All Intel E5000 PCIE ports */

			    || (bridge->vendor == PCI_VENDOR_ID_INTEL

				&& bridge->device >=