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Commit f19900b2 authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
Browse files

sh: remove old TMU driver 



This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c)

As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU
and configure timer channel using platform data.

If multiple TMU channels are enabled using platform data, use the
earlytimer parameter on the kernel command line to select channel.
For instance, use "earlytimer=sh_tmu.0" to select the first channel.

To verify which timer is being used, look at printouts or the timer
irq count in /proc/interrupts.

Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 2b23a882

arch/sh/Kconfig

+1 −8
Original line number Diff line number Diff line
@@ -473,16 +473,9 @@ source "arch/sh/boards/Kconfig" 


menu "Timer and clock configuration"



config SH_TMU

	bool "TMU timer support"

	depends on CPU_SH3 || CPU_SH4

	default y

	help

	  This enables the use of the TMU as the system timer.



config SH_TIMER_TMU

	bool "TMU timer driver"

	depends on !SH_TMU && SYS_SUPPORTS_TMU

	depends on SYS_SUPPORTS_TMU

	default y

	help

	  This enables the build of the TMU timer driver.

arch/sh/include/asm/timer.h

+0 −1
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ struct sys_timer { 
	struct sys_timer_ops	*ops;

};



extern struct sys_timer tmu_timer;

extern struct sys_timer *sys_timer;



/* arch/sh/kernel/timers/timer.c */

arch/sh/include/cpu-sh3/cpu/timer.h

deleted100644 → 0
+0 −67
Original line number Diff line number Diff line 
/*

 * include/asm-sh/cpu-sh3/timer.h

 *

 * Copyright (C) 2004 Lineo Solutions, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef __ASM_CPU_SH3_TIMER_H

#define __ASM_CPU_SH3_TIMER_H



/*

 * ---------------------------------------------------------------------------

 * TMU Common definitions for SH3 processors

 *	SH7706

 *	SH7709S

 *	SH7727

 *	SH7729R

 *	SH7710

 *	SH7720

 *	SH7710

 * ---------------------------------------------------------------------------

 */



#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)

#define TMU_TOCR	0xfffffe90	/* Byte access */

#endif



#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \

    defined(CONFIG_CPU_SUBTYPE_SH7720) || \

    defined(CONFIG_CPU_SUBTYPE_SH7721)

#define TMU_012_TSTR	0xa412fe92	/* Byte access */



#define TMU0_TCOR	0xa412fe94	/* Long access */

#define TMU0_TCNT	0xa412fe98	/* Long access */

#define TMU0_TCR	0xa412fe9c	/* Word access */



#define TMU1_TCOR	0xa412fea0	/* Long access */

#define TMU1_TCNT	0xa412fea4	/* Long access */

#define TMU1_TCR	0xa412fea8	/* Word access */



#define TMU2_TCOR	0xa412feac	/* Long access */

#define TMU2_TCNT	0xa412feb0	/* Long access */

#define TMU2_TCR	0xa412feb4	/* Word access */



#else

#define TMU_012_TSTR	0xfffffe92	/* Byte access */



#define TMU0_TCOR	0xfffffe94	/* Long access */

#define TMU0_TCNT	0xfffffe98	/* Long access */

#define TMU0_TCR	0xfffffe9c	/* Word access */



#define TMU1_TCOR	0xfffffea0	/* Long access */

#define TMU1_TCNT	0xfffffea4	/* Long access */

#define TMU1_TCR	0xfffffea8	/* Word access */



#define TMU2_TCOR	0xfffffeac	/* Long access */

#define TMU2_TCNT	0xfffffeb0	/* Long access */

#define TMU2_TCR	0xfffffeb4	/* Word access */

#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)

#define TMU2_TCPR2	0xfffffeb8	/* Long access */

#endif

#endif



#endif /* __ASM_CPU_SH3_TIMER_H */

arch/sh/include/cpu-sh4/cpu/timer.h

deleted100644 → 0
+0 −60
Original line number Diff line number Diff line 
/*

 * include/asm-sh/cpu-sh4/timer.h

 *

 * Copyright (C) 2004 Lineo Solutions, Inc.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef __ASM_CPU_SH4_TIMER_H

#define __ASM_CPU_SH4_TIMER_H



/*

 * ---------------------------------------------------------------------------

 * TMU Common definitions for SH4 processors

 *	SH7750S/SH7750R

 *	SH7751/SH7751R

 *	SH7760

 *	SH-X3

 * ---------------------------------------------------------------------------

 */

#ifdef CONFIG_CPU_SUBTYPE_SHX3

#define TMU_012_BASE	0xffc10000

#define TMU_345_BASE	0xffc20000

#else

#define TMU_012_BASE	0xffd80000

#define TMU_345_BASE	0xfe100000

#endif



#define TMU_TOCR	TMU_012_BASE	/* Not supported on all CPUs */



#define TMU_012_TSTR	(TMU_012_BASE + 0x04)

#define TMU_345_TSTR	(TMU_345_BASE + 0x04)



#define TMU0_TCOR	(TMU_012_BASE + 0x08)

#define TMU0_TCNT	(TMU_012_BASE + 0x0c)

#define TMU0_TCR	(TMU_012_BASE + 0x10)



#define TMU1_TCOR       (TMU_012_BASE + 0x14)

#define TMU1_TCNT       (TMU_012_BASE + 0x18)

#define TMU1_TCR        (TMU_012_BASE + 0x1c)



#define TMU2_TCOR       (TMU_012_BASE + 0x20)

#define TMU2_TCNT       (TMU_012_BASE + 0x24)

#define TMU2_TCR	(TMU_012_BASE + 0x28)

#define TMU2_TCPR	(TMU_012_BASE + 0x2c)



#define TMU3_TCOR	(TMU_345_BASE + 0x08)

#define TMU3_TCNT	(TMU_345_BASE + 0x0c)

#define TMU3_TCR	(TMU_345_BASE + 0x10)



#define TMU4_TCOR	(TMU_345_BASE + 0x14)

#define TMU4_TCNT	(TMU_345_BASE + 0x18)

#define TMU4_TCR	(TMU_345_BASE + 0x1c)



#define TMU5_TCOR	(TMU_345_BASE + 0x20)

#define TMU5_TCNT	(TMU_345_BASE + 0x24)

#define TMU5_TCR	(TMU_345_BASE + 0x28)



#endif /* __ASM_CPU_SH4_TIMER_H */

arch/sh/kernel/timers/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -3,5 +3,3 @@ 
#



obj-y	:= timer.o
 


obj-$(CONFIG_SH_TMU)		+= timer-tmu.o