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Commit f19786f9 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'samsung-drivers-4.8-2' of... 

Merge tag 'samsung-drivers-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers

Samsung drivers/soc update for v4.8, part 2:
1. Endian-friendly fixes.
2. Make SROMC driver explicitly non-module.

* tag 'samsung-drivers-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux

:
  cpufreq: s5pv210: use relaxed IO accesors
  memory: samsung: exynos-srom: make it explicitly non-modular
  memory: samsung: endian fixes for IO

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7cd4837e 187364b6

drivers/cpufreq/s5pv210-cpufreq.c

+34 −34
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) 


	tmp1 /= tmp;



	__raw_writel(tmp1, reg);

	writel_relaxed(tmp1, reg);

}



static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
@@ -301,29 +301,29 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
		 * 1. Temporary Change divider for MFC and G3D

		 * SCLKA2M(200/1=200)->(200/4=50)Mhz

		 */

		reg = __raw_readl(S5P_CLK_DIV2);

		reg = readl_relaxed(S5P_CLK_DIV2);

		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);

		reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |

			(3 << S5P_CLKDIV2_MFC_SHIFT);

		__raw_writel(reg, S5P_CLK_DIV2);

		writel_relaxed(reg, S5P_CLK_DIV2);



		/* For MFC, G3D dividing */

		do {

			reg = __raw_readl(S5P_CLKDIV_STAT0);

			reg = readl_relaxed(S5P_CLKDIV_STAT0);

		} while (reg & ((1 << 16) | (1 << 17)));



		/*

		 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX

		 * (200/4=50)->(667/4=166)Mhz

		 */

		reg = __raw_readl(S5P_CLK_SRC2);

		reg = readl_relaxed(S5P_CLK_SRC2);

		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);

		reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |

			(1 << S5P_CLKSRC2_MFC_SHIFT);

		__raw_writel(reg, S5P_CLK_SRC2);

		writel_relaxed(reg, S5P_CLK_SRC2);



		do {

			reg = __raw_readl(S5P_CLKMUX_STAT1);

			reg = readl_relaxed(S5P_CLKMUX_STAT1);

		} while (reg & ((1 << 7) | (1 << 3)));



		/*
@@ -335,19 +335,19 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
			s5pv210_set_refresh(DMC1, 133000);



		/* 4. SCLKAPLL -> SCLKMPLL */

		reg = __raw_readl(S5P_CLK_SRC0);

		reg = readl_relaxed(S5P_CLK_SRC0);

		reg &= ~(S5P_CLKSRC0_MUX200_MASK);

		reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);

		__raw_writel(reg, S5P_CLK_SRC0);

		writel_relaxed(reg, S5P_CLK_SRC0);



		do {

			reg = __raw_readl(S5P_CLKMUX_STAT0);

			reg = readl_relaxed(S5P_CLKMUX_STAT0);

		} while (reg & (0x1 << 18));



	}



	/* Change divider */

	reg = __raw_readl(S5P_CLK_DIV0);

	reg = readl_relaxed(S5P_CLK_DIV0);



	reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |

		S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
@@ -363,25 +363,25 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
		(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |

		(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));



	__raw_writel(reg, S5P_CLK_DIV0);

	writel_relaxed(reg, S5P_CLK_DIV0);



	do {

		reg = __raw_readl(S5P_CLKDIV_STAT0);

		reg = readl_relaxed(S5P_CLKDIV_STAT0);

	} while (reg & 0xff);



	/* ARM MCS value changed */

	reg = __raw_readl(S5P_ARM_MCS_CON);

	reg = readl_relaxed(S5P_ARM_MCS_CON);

	reg &= ~0x3;

	if (index >= L3)

		reg |= 0x3;

	else

		reg |= 0x1;



	__raw_writel(reg, S5P_ARM_MCS_CON);

	writel_relaxed(reg, S5P_ARM_MCS_CON);



	if (pll_changing) {

		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */

		__raw_writel(0x2cf, S5P_APLL_LOCK);

		writel_relaxed(0x2cf, S5P_APLL_LOCK);



		/*

		 * 6. Turn on APLL
@@ -389,12 +389,12 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
		 * 6-2. Wait untile the PLL is locked

		 */

		if (index == L0)

			__raw_writel(APLL_VAL_1000, S5P_APLL_CON);

			writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);

		else

			__raw_writel(APLL_VAL_800, S5P_APLL_CON);

			writel_relaxed(APLL_VAL_800, S5P_APLL_CON);



		do {

			reg = __raw_readl(S5P_APLL_CON);

			reg = readl_relaxed(S5P_APLL_CON);

		} while (!(reg & (0x1 << 29)));



		/*
@@ -402,39 +402,39 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX

		 * (667/4=166)->(200/4=50)Mhz

		 */

		reg = __raw_readl(S5P_CLK_SRC2);

		reg = readl_relaxed(S5P_CLK_SRC2);

		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);

		reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |

			(0 << S5P_CLKSRC2_MFC_SHIFT);

		__raw_writel(reg, S5P_CLK_SRC2);

		writel_relaxed(reg, S5P_CLK_SRC2);



		do {

			reg = __raw_readl(S5P_CLKMUX_STAT1);

			reg = readl_relaxed(S5P_CLKMUX_STAT1);

		} while (reg & ((1 << 7) | (1 << 3)));



		/*

		 * 8. Change divider for MFC and G3D

		 * (200/4=50)->(200/1=200)Mhz

		 */

		reg = __raw_readl(S5P_CLK_DIV2);

		reg = readl_relaxed(S5P_CLK_DIV2);

		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);

		reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |

			(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);

		__raw_writel(reg, S5P_CLK_DIV2);

		writel_relaxed(reg, S5P_CLK_DIV2);



		/* For MFC, G3D dividing */

		do {

			reg = __raw_readl(S5P_CLKDIV_STAT0);

			reg = readl_relaxed(S5P_CLKDIV_STAT0);

		} while (reg & ((1 << 16) | (1 << 17)));



		/* 9. Change MPLL to APLL in MSYS_MUX */

		reg = __raw_readl(S5P_CLK_SRC0);

		reg = readl_relaxed(S5P_CLK_SRC0);

		reg &= ~(S5P_CLKSRC0_MUX200_MASK);

		reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);

		__raw_writel(reg, S5P_CLK_SRC0);

		writel_relaxed(reg, S5P_CLK_SRC0);



		do {

			reg = __raw_readl(S5P_CLKMUX_STAT0);

			reg = readl_relaxed(S5P_CLKMUX_STAT0);

		} while (reg & (0x1 << 18));



		/*
@@ -451,13 +451,13 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 
	 * and memory refresh parameter should be changed

	 */

	if (bus_speed_changing) {

		reg = __raw_readl(S5P_CLK_DIV6);

		reg = readl_relaxed(S5P_CLK_DIV6);

		reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;

		reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);

		__raw_writel(reg, S5P_CLK_DIV6);

		writel_relaxed(reg, S5P_CLK_DIV6);



		do {

			reg = __raw_readl(S5P_CLKDIV_STAT1);

			reg = readl_relaxed(S5P_CLKDIV_STAT1);

		} while (reg & (1 << 15));



		/* Reconfigure DRAM refresh counter value */
@@ -497,7 +497,7 @@ static int check_mem_type(void __iomem *dmc_reg) 
{

	unsigned long val;



	val = __raw_readl(dmc_reg + 0x4);

	val = readl_relaxed(dmc_reg + 0x4);

	val = (val & (0xf << 8));



	return val >> 8;
@@ -542,10 +542,10 @@ static int s5pv210_cpu_init(struct cpufreq_policy *policy) 
	}



	/* Find current refresh counter and frequency each DMC */

	s5pv210_dram_conf[0].refresh = (__raw_readl(dmc_base[0] + 0x30) * 1000);

	s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);

	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);



	s5pv210_dram_conf[1].refresh = (__raw_readl(dmc_base[1] + 0x30) * 1000);

	s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);

	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);



	policy->suspend_freq = SLEEP_FREQ;

drivers/memory/samsung/exynos-srom.c

+12 −27
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
 */



#include <linux/io.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>
@@ -91,11 +91,11 @@ static int exynos_srom_configure_bank(struct exynos_srom *srom, 
	if (width == 2)

		cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;



	bw = __raw_readl(srom->reg_base + EXYNOS_SROM_BW);

	bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);

	bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);

	__raw_writel(bw, srom->reg_base + EXYNOS_SROM_BW);

	writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);



	__raw_writel(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |

	writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |

		       (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |

		       (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |

		       (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
@@ -159,16 +159,6 @@ static int exynos_srom_probe(struct platform_device *pdev) 
	return of_platform_populate(np, NULL, NULL, dev);

}



static int exynos_srom_remove(struct platform_device *pdev)

{

	struct exynos_srom *srom = platform_get_drvdata(pdev);



	kfree(srom->reg_offset);

	iounmap(srom->reg_base);



	return 0;

}



#ifdef CONFIG_PM_SLEEP

static void exynos_srom_save(void __iomem *base,

				    struct exynos_srom_reg_dump *rd,
@@ -211,21 +201,16 @@ static const struct of_device_id of_exynos_srom_ids[] = { 
	},

	{},

};

MODULE_DEVICE_TABLE(of, of_exynos_srom_ids);



static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);



static struct platform_driver exynos_srom_driver = {

	.probe = exynos_srom_probe,

	.remove = exynos_srom_remove,

	.driver = {

		.name = "exynos-srom",

		.of_match_table = of_exynos_srom_ids,

		.pm = &exynos_srom_pm_ops,

		.suppress_bind_attrs = true,

	},

};

module_platform_driver(exynos_srom_driver);



MODULE_AUTHOR("Pankaj Dubey <pankaj.dubey@samsung.com>");

MODULE_DESCRIPTION("Exynos SROM Controller Driver");

MODULE_LICENSE("GPL");
 
builtin_platform_driver(exynos_srom_driver);