clk: shmobile: rz: Add CPG/MSTP Clock Domain support

The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable

CPU and GPU clocks, and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.

Required Properties:

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "pll",

    "i", and "g"

  - #power-domain-cells: Must be 0

SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.

Example

-------

Examples

--------

  - CPG device node:

	cpg_clocks: cpg_clocks@fcfe0000 {

		#clock-cells = <1>;

		reg = <0xfcfe0000 0x18>;

		clocks = <&extal_clk>, <&usb_x1_clk>;

		clock-output-names = "pll", "i", "g";

		#power-domain-cells = <0>;

	};

  - CPG/MSTP Clock Domain member device node:

	mtu2: timer@fcff0000 {

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		reg = <0xfcff0000 0x400>;

		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};

config ARCH_R7S72100

	bool "RZ/A1H (R7S72100)"

	select PM_GENERIC_DOMAINS if PM

	select SYS_SUPPORTS_SH_MTU2

config ARCH_R8A73A4

 */

#include <linux/clk-provider.h>

#include <linux/clk/shmobile.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/of.h>

	}

	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

	cpg_mstp_add_clk_domain(np);

}

CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);