Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ee71c2f9 authored by Stefan Richter's avatar Stefan Richter
Browse files

firewire: fw-ohci: enforce read order for selfID generation 



It seems unlikely, but access to self_id_cpu[0] could at least in theory
be deferred until after the loop over self_id_cpu[1..n] or even after
the subsequent reg_read.  Enforce the desired order by a read barrier.

Also prevent the reg_read from being reordered relative to the for loop.
This isn't necessary if the loop's conditional printk counts as an
implicit barrier, but better make it explicit.

(self_id_cpu[] is a coherent DMA buffer.)

Signed-off-by: default avatarStefan Richter <stefanr@s5r6.in-berlin.de>
parent df8ec249

drivers/firewire/fw-ohci.c

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 


#include <asm/uaccess.h>

#include <asm/semaphore.h>

#include <asm/system.h>



#include "fw-transaction.h"

#include "fw-ohci.h"
@@ -926,12 +927,14 @@ static void bus_reset_tasklet(unsigned long data) 


	self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;

	generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;

	rmb();



	for (i = 1, j = 0; j < self_id_count; i += 2, j++) {

		if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])

			fw_error("inconsistent self IDs\n");

		ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);

	}

	rmb();



	/*

	 * Check the consistency of the self IDs we just read.  The