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Commit ee58fad5 authored by Stephane Eranian's avatar Stephane Eranian Committed by Andi Kleen
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[PATCH] x86-64: x86-64 add Intel BTS cpufeature bit and detection (take 2) 



Here is a small patch for x86-64 which adds a cpufeature flag and
detection code for Intel's Branch Trace Store (BTS) feature. This
feature can be found on Intel P4 and Core 2 processors among others.
It can also be used by perfmon.

changelog:
	- add CPU_FEATURE_BTS
	- add Branch Trace Store detection

signed-off-by: default avatarstephane eranian <eranian@hpl.hp.com>

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent 7e95b593

arch/x86_64/kernel/setup.c

+2 −0
Original line number Diff line number Diff line
@@ -838,6 +838,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
	if (cpu_has_ds) {

		unsigned int l1, l2;

		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);

		if (!(l1 & (1<<11)))

			set_bit(X86_FEATURE_BTS, c->x86_capability);

		if (!(l1 & (1<<12)))

			set_bit(X86_FEATURE_PEBS, c->x86_capability);

	}

include/asm-x86_64/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ 
#define X86_FEATURE_UP		(3*32+8) /* SMP kernel running on UP */

#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */

#define X86_FEATURE_PEBS	(3*32+10) /* Precise-Event Based Sampling */

#define X86_FEATURE_BTS		(3*32+11) /* Branch Trace Store */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -115,5 +116,6 @@ 
#define cpu_has_clflush	       boot_cpu_has(X86_FEATURE_CLFLSH)

#define cpu_has_ds 	       boot_cpu_has(X86_FEATURE_DS)

#define cpu_has_pebs 	       boot_cpu_has(X86_FEATURE_PEBS)

#define cpu_has_bts 	       boot_cpu_has(X86_FEATURE_BTS)



#endif /* __ASM_X8664_CPUFEATURE_H */