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Commit edd2a06d authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'sunxi-clocks-for-4.4' of... 

Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt

Bringing in the sunxi clock branch since it introduces header file contents
that is needed by the DT branch. This is a stable tag shared with the clk tree.

Allwinner clock additions for 4.4

  - Support for the Audio PLL and child clocks
  - Support for the A33 AHB gates
  - New clk-multiplier generic driver

* tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux

:
  clk: sunxi: mod1 clock support
  clk: sunxi: codec clock support
  clk: sunxi: pll2: Add A13 support
  clk: sunxi: Add a driver for the PLL2
  clk: Add a basic multiplier clock
  clk: sunxi: Add A33 gates support

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 64ebda3a 9b038bc5

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-divider.o 
obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-factor.o

obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o

obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o

obj-$(CONFIG_COMMON_CLK)	+= clk-multiplier.o

obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o

obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o

obj-$(CONFIG_COMMON_CLK)	+= clk-fractional-divider.o

drivers/clk/clk-multiplier.c

0 → 100644
+181 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2015 Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/bitops.h>

#include <linux/clk-provider.h>

#include <linux/err.h>

#include <linux/export.h>

#include <linux/kernel.h>

#include <linux/of.h>

#include <linux/slab.h>



#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)



static unsigned long __get_mult(struct clk_multiplier *mult,

				unsigned long rate,

				unsigned long parent_rate)

{

	if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST)

		return DIV_ROUND_CLOSEST(rate, parent_rate);



	return rate / parent_rate;

}



static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,

						unsigned long parent_rate)

{

	struct clk_multiplier *mult = to_clk_multiplier(hw);

	unsigned long val;



	val = clk_readl(mult->reg) >> mult->shift;

	val &= GENMASK(mult->width - 1, 0);



	if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)

		val = 1;



	return parent_rate * val;

}



static bool __is_best_rate(unsigned long rate, unsigned long new,

			   unsigned long best, unsigned long flags)

{

	if (flags & CLK_MULTIPLIER_ROUND_CLOSEST)

		return abs(rate - new) < abs(rate - best);



	return new >= rate && new < best;

}



static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,

				unsigned long *best_parent_rate,

				u8 width, unsigned long flags)

{

	unsigned long orig_parent_rate = *best_parent_rate;

	unsigned long parent_rate, current_rate, best_rate = ~0;

	unsigned int i, bestmult = 0;



	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))

		return rate / *best_parent_rate;



	for (i = 1; i < ((1 << width) - 1); i++) {

		if (rate == orig_parent_rate * i) {

			/*

			 * This is the best case for us if we have a

			 * perfect match without changing the parent

			 * rate.

			 */

			*best_parent_rate = orig_parent_rate;

			return i;

		}



		parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),

						rate / i);

		current_rate = parent_rate * i;



		if (__is_best_rate(rate, current_rate, best_rate, flags)) {

			bestmult = i;

			best_rate = current_rate;

			*best_parent_rate = parent_rate;

		}

	}



	return bestmult;

}



static long clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate,

				  unsigned long *parent_rate)

{

	struct clk_multiplier *mult = to_clk_multiplier(hw);

	unsigned long factor = __bestmult(hw, rate, parent_rate,

					  mult->width, mult->flags);



	return *parent_rate * factor;

}



static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,

			       unsigned long parent_rate)

{

	struct clk_multiplier *mult = to_clk_multiplier(hw);

	unsigned long factor = __get_mult(mult, rate, parent_rate);

	unsigned long flags = 0;

	unsigned long val;



	if (mult->lock)

		spin_lock_irqsave(mult->lock, flags);

	else

		__acquire(mult->lock);



	val = clk_readl(mult->reg);

	val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);

	val |= factor << mult->shift;

	clk_writel(val, mult->reg);



	if (mult->lock)

		spin_unlock_irqrestore(mult->lock, flags);

	else

		__release(mult->lock);



	return 0;

}



const struct clk_ops clk_multiplier_ops = {

	.recalc_rate	= clk_multiplier_recalc_rate,

	.round_rate	= clk_multiplier_round_rate,

	.set_rate	= clk_multiplier_set_rate,

};

EXPORT_SYMBOL_GPL(clk_multiplier_ops);



struct clk *clk_register_multiplier(struct device *dev, const char *name,

				    const char *parent_name,

				    unsigned long flags,

				    void __iomem *reg, u8 shift, u8 width,

				    u8 clk_mult_flags, spinlock_t *lock)

{

	struct clk_init_data init;

	struct clk_multiplier *mult;

	struct clk *clk;



	mult = kmalloc(sizeof(*mult), GFP_KERNEL);

	if (!mult)

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.ops = &clk_multiplier_ops;

	init.flags = flags | CLK_IS_BASIC;

	init.parent_names = &parent_name;

	init.num_parents = 1;



	mult->reg = reg;

	mult->shift = shift;

	mult->width = width;

	mult->flags = clk_mult_flags;

	mult->lock = lock;

	mult->hw.init = &init;



	clk = clk_register(dev, &mult->hw);

	if (IS_ERR(clk))

		kfree(mult);



	return clk;

}

EXPORT_SYMBOL_GPL(clk_register_multiplier);



void clk_unregister_multiplier(struct clk *clk)

{

	struct clk_multiplier *mult;

	struct clk_hw *hw;



	hw = __clk_get_hw(clk);

	if (!hw)

		return;



	mult = to_clk_multiplier(hw);



	clk_unregister(clk);

	kfree(mult);

}

EXPORT_SYMBOL_GPL(clk_unregister_multiplier);

drivers/clk/sunxi/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -3,7 +3,10 @@ 
#



obj-y += clk-sunxi.o clk-factors.o

obj-y += clk-a10-codec.o

obj-y += clk-a10-hosc.o

obj-y += clk-a10-mod1.o

obj-y += clk-a10-pll2.o

obj-y += clk-a20-gmac.o

obj-y += clk-mod0.o

obj-y += clk-simple-gates.o

drivers/clk/sunxi/clk-a10-codec.c

0 → 100644
+44 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Emilio López

 *

 * Emilio López <emilio@elopez.com.ar>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>



#define SUN4I_CODEC_GATE	31



static void __init sun4i_codec_clk_setup(struct device_node *node)

{

	struct clk *clk;

	const char *clk_name = node->name, *parent_name;

	void __iomem *reg;



	reg = of_io_request_and_map(node, 0, of_node_full_name(node));

	if (IS_ERR(reg))

		return;



	of_property_read_string(node, "clock-output-names", &clk_name);

	parent_name = of_clk_get_parent_name(node, 0);



	clk = clk_register_gate(NULL, clk_name, parent_name,

				CLK_SET_RATE_PARENT, reg,

				SUN4I_CODEC_GATE, 0, NULL);



	if (!IS_ERR(clk))

		of_clk_add_provider(node, of_clk_src_simple_get, clk);

}

CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk",

	       sun4i_codec_clk_setup);

drivers/clk/sunxi/clk-a10-mod1.c

0 → 100644
+81 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Emilio López

 *

 * Emilio López <emilio@elopez.com.ar>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/slab.h>



static DEFINE_SPINLOCK(mod1_lock);



#define SUN4I_MOD1_ENABLE	31

#define SUN4I_MOD1_MUX		16

#define SUN4I_MOD1_MUX_WIDTH	2

#define SUN4I_MOD1_MAX_PARENTS	4



static void __init sun4i_mod1_clk_setup(struct device_node *node)

{

	struct clk *clk;

	struct clk_mux *mux;

	struct clk_gate *gate;

	const char *parents[4];

	const char *clk_name = node->name;

	void __iomem *reg;

	int i;



	reg = of_io_request_and_map(node, 0, of_node_full_name(node));

	if (IS_ERR(reg))

		return;



	mux = kzalloc(sizeof(*mux), GFP_KERNEL);

	if (!mux)

		goto err_unmap;



	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate)

		goto err_free_mux;



	of_property_read_string(node, "clock-output-names", &clk_name);

	i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);



	gate->reg = reg;

	gate->bit_idx = SUN4I_MOD1_ENABLE;

	gate->lock = &mod1_lock;

	mux->reg = reg;

	mux->shift = SUN4I_MOD1_MUX;

	mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;

	mux->lock = &mod1_lock;



	clk = clk_register_composite(NULL, clk_name, parents, i,

				     &mux->hw, &clk_mux_ops,

				     NULL, NULL,

				     &gate->hw, &clk_gate_ops, 0);

	if (IS_ERR(clk))

		goto err_free_gate;



	of_clk_add_provider(node, of_clk_src_simple_get, clk);



	return;



err_free_gate:

	kfree(gate);

err_free_mux:

	kfree(mux);

err_unmap:

	iounmap(reg);

}

CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",

	       sun4i_mod1_clk_setup);