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Commit ed7d6bc2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-next-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending 

Pull more SCSI target updates from Nicholas Bellinger:
 "This series contains cxgb4 driver prerequisites for supporting iscsi
  segmentation offload (ISO), that will be utilized for a number of
  future v4.7 developments in iscsi-target for supporting generic hw
  offloads"

* 'for-next-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending:
  cxgb4: update Kconfig and Makefile
  cxgb4: add iSCSI DDP page pod manager
  cxgb4, iw_cxgb4: move delayed ack macro definitions
  cxgb4: move VLAN_NONE macro definition
  cxgb4: update struct cxgb4_lld_info definition
  cxgb4: add definitions for iSCSI target ULD
  cxgb4, cxgb4i: move struct cpl_rx_data_ddp definition
  cxgb4, iw_cxgb4, cxgb4i: remove duplicate definitions
  cxgb4, iw_cxgb4: move definitions to common header file
  cxgb4: large receive offload support
  cxgb4: allocate resources for CXGB4_ULD_ISCSIT
  cxgb4: add new ULD type CXGB4_ULD_ISCSIT
parents c1304236 2994a751

drivers/infiniband/hw/cxgb4/t4fw_ri_api.h

+0 −99
Original line number Diff line number Diff line
@@ -753,103 +753,4 @@ struct fw_ri_wr { 
#define FW_RI_WR_P2PTYPE_G(x)	\

	(((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M)



struct tcp_options {

	__be16 mss;

	__u8 wsf;

#if defined(__LITTLE_ENDIAN_BITFIELD)

	__u8:4;

	__u8 unknown:1;

	__u8:1;

	__u8 sack:1;

	__u8 tstamp:1;

#else

	__u8 tstamp:1;

	__u8 sack:1;

	__u8:1;

	__u8 unknown:1;

	__u8:4;

#endif

};



struct cpl_pass_accept_req {

	union opcode_tid ot;

	__be16 rsvd;

	__be16 len;

	__be32 hdr_len;

	__be16 vlan;

	__be16 l2info;

	__be32 tos_stid;

	struct tcp_options tcpopt;

};



/* cpl_pass_accept_req.hdr_len fields */

#define SYN_RX_CHAN_S    0

#define SYN_RX_CHAN_M    0xF

#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)

#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)



#define TCP_HDR_LEN_S    10

#define TCP_HDR_LEN_M    0x3F

#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)

#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)



#define IP_HDR_LEN_S    16

#define IP_HDR_LEN_M    0x3FF

#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)

#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)



#define ETH_HDR_LEN_S    26

#define ETH_HDR_LEN_M    0x1F

#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)

#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)



/* cpl_pass_accept_req.l2info fields */

#define SYN_MAC_IDX_S    0

#define SYN_MAC_IDX_M    0x1FF

#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)

#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)



#define SYN_XACT_MATCH_S    9

#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)

#define SYN_XACT_MATCH_F    SYN_XACT_MATCH_V(1U)



#define SYN_INTF_S    12

#define SYN_INTF_M    0xF

#define SYN_INTF_V(x) ((x) << SYN_INTF_S)

#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)



struct ulptx_idata {

	__be32 cmd_more;

	__be32 len;

};



#define ULPTX_NSGE_S    0

#define ULPTX_NSGE_M    0xFFFF

#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)



#define RX_DACK_MODE_S    29

#define RX_DACK_MODE_M    0x3

#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)

#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)



#define RX_DACK_CHANGE_S    31

#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)

#define RX_DACK_CHANGE_F    RX_DACK_CHANGE_V(1U)



enum {                     /* TCP congestion control algorithms */

	CONG_ALG_RENO,

	CONG_ALG_TAHOE,

	CONG_ALG_NEWRENO,

	CONG_ALG_HIGHSPEED

};



#define CONG_CNTRL_S    14

#define CONG_CNTRL_M    0x3

#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)

#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)



#define T5_ISS_S    18

#define T5_ISS_V(x) ((x) << T5_ISS_S)

#define T5_ISS_F    T5_ISS_V(1U)



#endif /* _T4FW_RI_API_H_ */

drivers/net/ethernet/chelsio/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -96,6 +96,17 @@ config CHELSIO_T4_DCB 


	  If unsure, say N.



config CHELSIO_T4_UWIRE

	bool "Unified Wire Support for Chelsio T5 cards"

	default n

	depends on CHELSIO_T4

	---help---

	  Enable unified-wire offload features.

	  Say Y here if you want to enable unified-wire over Ethernet

	  in the driver.



	  If unsure, say N.



config CHELSIO_T4_FCOE

	bool "Fibre Channel over Ethernet (FCoE) Support for Chelsio T5 cards"

	default n

drivers/net/ethernet/chelsio/cxgb4/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,4 +7,5 @@ obj-$(CONFIG_CHELSIO_T4) += cxgb4.o 
cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o

cxgb4-$(CONFIG_CHELSIO_T4_DCB) +=  cxgb4_dcb.o

cxgb4-$(CONFIG_CHELSIO_T4_FCOE) +=  cxgb4_fcoe.o

cxgb4-$(CONFIG_CHELSIO_T4_UWIRE) +=  cxgb4_ppm.o

cxgb4-$(CONFIG_DEBUG_FS) += cxgb4_debugfs.o

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

+24 −3
Original line number Diff line number Diff line
@@ -404,6 +404,9 @@ enum { 
	MAX_CTRL_QUEUES = NCHAN,      /* # of control Tx queues */

	MAX_RDMA_QUEUES = NCHAN,      /* # of streaming RDMA Rx queues */

	MAX_RDMA_CIQS = 32,        /* # of  RDMA concentrator IQs */



	/* # of streaming iSCSIT Rx queues */

	MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,

};



enum {
@@ -420,8 +423,8 @@ enum { 
enum {

	INGQ_EXTRAS = 2,        /* firmware event queue and */

				/*   forwarded interrupts */

	MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES

		   + MAX_RDMA_CIQS + INGQ_EXTRAS,

	MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +

		   MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,

};



struct adapter;
@@ -508,6 +511,15 @@ struct pkt_gl { 


typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,

			      const struct pkt_gl *gl);

typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);

/* LRO related declarations for ULD */

struct t4_lro_mgr {

#define MAX_LRO_SESSIONS		64

	u8 lro_session_cnt;         /* # of sessions to aggregate */

	unsigned long lro_pkts;     /* # of LRO super packets */

	unsigned long lro_merged;   /* # of wire packets merged by LRO */

	struct sk_buff_head lroq;   /* list of aggregated sessions */

};



struct sge_rspq {                   /* state for an SGE response queue */

	struct napi_struct napi;
@@ -532,6 +544,8 @@ struct sge_rspq { /* state for an SGE response queue */ 
	struct adapter *adap;

	struct net_device *netdev;  /* associated net device */

	rspq_handler_t handler;

	rspq_flush_handler_t flush_handler;

	struct t4_lro_mgr lro_mgr;

#ifdef CONFIG_NET_RX_BUSY_POLL

#define CXGB_POLL_STATE_IDLE		0

#define CXGB_POLL_STATE_NAPI		BIT(0) /* NAPI owns this poll */
@@ -641,6 +655,7 @@ struct sge { 


	struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];

	struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];

	struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];

	struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];

	struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];

	struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
@@ -652,9 +667,11 @@ struct sge { 
	u16 ethqsets;               /* # of active Ethernet queue sets */

	u16 ethtxq_rover;           /* Tx queue to clean up next */

	u16 iscsiqsets;              /* # of active iSCSI queue sets */

	u16 niscsitq;               /* # of available iSCST Rx queues */

	u16 rdmaqs;                 /* # of available RDMA Rx queues */

	u16 rdmaciqs;               /* # of available RDMA concentrator IQs */

	u16 iscsi_rxq[MAX_OFLD_QSETS];

	u16 iscsit_rxq[MAX_ISCSIT_QUEUES];

	u16 rdma_rxq[MAX_RDMA_QUEUES];

	u16 rdma_ciq[MAX_RDMA_CIQS];

	u16 timer_val[SGE_NTIMERS];
@@ -681,6 +698,7 @@ struct sge { 


#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)

#define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)

#define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)

#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)

#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
@@ -747,6 +765,8 @@ struct adapter { 
	struct list_head rcu_node;

	struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */



	void *iscsi_ppm;



	struct tid_info tids;

	void **tid_release_head;

	spinlock_t tid_release_lock;
@@ -1113,7 +1133,8 @@ int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 
int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);

int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,

		     struct net_device *dev, int intr_idx,

		     struct sge_fl *fl, rspq_handler_t hnd, int cong);

		     struct sge_fl *fl, rspq_handler_t hnd,

		     rspq_flush_handler_t flush_handler, int cong);

int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,

			 struct net_device *dev, struct netdev_queue *netdevq,

			 unsigned int iqid);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c

+33 −1
Original line number Diff line number Diff line
@@ -2334,12 +2334,14 @@ static int sge_qinfo_show(struct seq_file *seq, void *v) 
	struct adapter *adap = seq->private;

	int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4);

	int iscsi_entries = DIV_ROUND_UP(adap->sge.iscsiqsets, 4);

	int iscsit_entries = DIV_ROUND_UP(adap->sge.niscsitq, 4);

	int rdma_entries = DIV_ROUND_UP(adap->sge.rdmaqs, 4);

	int ciq_entries = DIV_ROUND_UP(adap->sge.rdmaciqs, 4);

	int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4);

	int i, r = (uintptr_t)v - 1;

	int iscsi_idx = r - eth_entries;

	int rdma_idx = iscsi_idx - iscsi_entries;

	int iscsit_idx = iscsi_idx - iscsi_entries;

	int rdma_idx = iscsit_idx - iscsit_entries;

	int ciq_idx = rdma_idx - rdma_entries;

	int ctrl_idx =  ciq_idx - ciq_entries;

	int fq_idx =  ctrl_idx - ctrl_entries;
@@ -2453,6 +2455,35 @@ do { \ 
		RL("FLLow:", fl.low);

		RL("FLStarving:", fl.starving);



	} else if (iscsit_idx < iscsit_entries) {

		const struct sge_ofld_rxq *rx =

			&adap->sge.iscsitrxq[iscsit_idx * 4];

		int n = min(4, adap->sge.niscsitq - 4 * iscsit_idx);



		S("QType:", "iSCSIT");

		R("RspQ ID:", rspq.abs_id);

		R("RspQ size:", rspq.size);

		R("RspQE size:", rspq.iqe_len);

		R("RspQ CIDX:", rspq.cidx);

		R("RspQ Gen:", rspq.gen);

		S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));

		S3("u", "Intr pktcnt:",

		   adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);

		R("FL ID:", fl.cntxt_id);

		R("FL size:", fl.size - 8);

		R("FL pend:", fl.pend_cred);

		R("FL avail:", fl.avail);

		R("FL PIDX:", fl.pidx);

		R("FL CIDX:", fl.cidx);

		RL("RxPackets:", stats.pkts);

		RL("RxImmPkts:", stats.imm);

		RL("RxNoMem:", stats.nomem);

		RL("FLAllocErr:", fl.alloc_failed);

		RL("FLLrgAlcErr:", fl.large_alloc_failed);

		RL("FLMapErr:", fl.mapping_err);

		RL("FLLow:", fl.low);

		RL("FLStarving:", fl.starving);



	} else if (rdma_idx < rdma_entries) {

		const struct sge_ofld_rxq *rx =

				&adap->sge.rdmarxq[rdma_idx * 4];
@@ -2543,6 +2574,7 @@ static int sge_queue_entries(const struct adapter *adap) 
{

	return DIV_ROUND_UP(adap->sge.ethqsets, 4) +

	       DIV_ROUND_UP(adap->sge.iscsiqsets, 4) +

	       DIV_ROUND_UP(adap->sge.niscsitq, 4) +

	       DIV_ROUND_UP(adap->sge.rdmaqs, 4) +

	       DIV_ROUND_UP(adap->sge.rdmaciqs, 4) +

	       DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1;