Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ec8f5d8f authored by Stanimir Varbanov's avatar Stanimir Varbanov Committed by Herbert Xu
Browse files

crypto: qce - Qualcomm crypto engine driver 



The driver is separated by functional parts. The core part
implements a platform driver probe and remove callbaks.
The probe enables clocks, checks crypto version, initialize
and request dma channels, create done tasklet and init
crypto queue and finally register the algorithms into crypto
core subsystem.

- DMA and SG helper functions
 implement dmaengine and sg-list helper functions used by
 other parts of the crypto driver.

- ablkcipher algorithms
 implementation of AES, DES and 3DES crypto API callbacks,
 the crypto register alg function, the async request handler
 and its dma done callback function.

- SHA and HMAC transforms
 implementation and registration of ahash crypto type.
 It includes sha1, sha256, hmac(sha1) and hmac(sha256).

- infrastructure to setup the crypto hw
 contains functions used to setup/prepare hardware registers for
 all algorithms supported by the crypto block. It also exports
 few helper functions needed by algorithms:
	- to check hardware status
	- to start crypto hardware
	- to translate data stream to big endian form

 Adds register addresses and bit/masks used by the driver
 as well.

Signed-off-by: default avatarStanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 002c77a4

drivers/crypto/qce/ablkcipher.c

0 → 100644
+431 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/device.h>

#include <linux/interrupt.h>

#include <linux/types.h>

#include <crypto/aes.h>

#include <crypto/algapi.h>

#include <crypto/des.h>



#include "cipher.h"



static LIST_HEAD(ablkcipher_algs);



static void qce_ablkcipher_done(void *data)

{

	struct crypto_async_request *async_req = data;

	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);

	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);

	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);

	struct qce_device *qce = tmpl->qce;

	enum dma_data_direction dir_src, dir_dst;

	u32 status;

	int error;

	bool diff_dst;



	diff_dst = (req->src != req->dst) ? true : false;

	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;

	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;



	error = qce_dma_terminate_all(&qce->dma);

	if (error)

		dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n",

			error);



	if (diff_dst)

		qce_unmapsg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src,

			    rctx->dst_chained);

	qce_unmapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst,

		    rctx->dst_chained);



	sg_free_table(&rctx->dst_tbl);



	error = qce_check_status(qce, &status);

	if (error < 0)

		dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status);



	qce->async_req_done(tmpl->qce, error);

}



static int

qce_ablkcipher_async_req_handle(struct crypto_async_request *async_req)

{

	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);

	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);

	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);

	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);

	struct qce_device *qce = tmpl->qce;

	enum dma_data_direction dir_src, dir_dst;

	struct scatterlist *sg;

	bool diff_dst;

	gfp_t gfp;

	int ret;



	rctx->iv = req->info;

	rctx->ivsize = crypto_ablkcipher_ivsize(ablkcipher);

	rctx->cryptlen = req->nbytes;



	diff_dst = (req->src != req->dst) ? true : false;

	dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL;

	dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;



	rctx->src_nents = qce_countsg(req->src, req->nbytes,

				      &rctx->src_chained);

	if (diff_dst) {

		rctx->dst_nents = qce_countsg(req->dst, req->nbytes,

					      &rctx->dst_chained);

	} else {

		rctx->dst_nents = rctx->src_nents;

		rctx->dst_chained = rctx->src_chained;

	}



	rctx->dst_nents += 1;



	gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?

						GFP_KERNEL : GFP_ATOMIC;



	ret = sg_alloc_table(&rctx->dst_tbl, rctx->dst_nents, gfp);

	if (ret)

		return ret;



	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);



	sg = qce_sgtable_add(&rctx->dst_tbl, req->dst);

	if (IS_ERR(sg)) {

		ret = PTR_ERR(sg);

		goto error_free;

	}



	sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg);

	if (IS_ERR(sg)) {

		ret = PTR_ERR(sg);

		goto error_free;

	}



	sg_mark_end(sg);

	rctx->dst_sg = rctx->dst_tbl.sgl;



	ret = qce_mapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst,

			rctx->dst_chained);

	if (ret < 0)

		goto error_free;



	if (diff_dst) {

		ret = qce_mapsg(qce->dev, req->src, rctx->src_nents, dir_src,

				rctx->src_chained);

		if (ret < 0)

			goto error_unmap_dst;

		rctx->src_sg = req->src;

	} else {

		rctx->src_sg = rctx->dst_sg;

	}



	ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,

			       rctx->dst_sg, rctx->dst_nents,

			       qce_ablkcipher_done, async_req);

	if (ret)

		goto error_unmap_src;



	qce_dma_issue_pending(&qce->dma);



	ret = qce_start(async_req, tmpl->crypto_alg_type, req->nbytes, 0);

	if (ret)

		goto error_terminate;



	return 0;



error_terminate:

	qce_dma_terminate_all(&qce->dma);

error_unmap_src:

	if (diff_dst)

		qce_unmapsg(qce->dev, req->src, rctx->src_nents, dir_src,

			    rctx->src_chained);

error_unmap_dst:

	qce_unmapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst,

		    rctx->dst_chained);

error_free:

	sg_free_table(&rctx->dst_tbl);

	return ret;

}



static int qce_ablkcipher_setkey(struct crypto_ablkcipher *ablk, const u8 *key,

				 unsigned int keylen)

{

	struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk);

	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);

	unsigned long flags = to_cipher_tmpl(tfm)->alg_flags;

	int ret;



	if (!key || !keylen)

		return -EINVAL;



	if (IS_AES(flags)) {

		switch (keylen) {

		case AES_KEYSIZE_128:

		case AES_KEYSIZE_256:

			break;

		default:

			goto fallback;

		}

	} else if (IS_DES(flags)) {

		u32 tmp[DES_EXPKEY_WORDS];



		ret = des_ekey(tmp, key);

		if (!ret && crypto_ablkcipher_get_flags(ablk) &

		    CRYPTO_TFM_REQ_WEAK_KEY)

			goto weakkey;

	}



	ctx->enc_keylen = keylen;

	memcpy(ctx->enc_key, key, keylen);

	return 0;

fallback:

	ret = crypto_ablkcipher_setkey(ctx->fallback, key, keylen);

	if (!ret)

		ctx->enc_keylen = keylen;

	return ret;

weakkey:

	crypto_ablkcipher_set_flags(ablk, CRYPTO_TFM_RES_WEAK_KEY);

	return -EINVAL;

}



static int qce_ablkcipher_crypt(struct ablkcipher_request *req, int encrypt)

{

	struct crypto_tfm *tfm =

			crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));

	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);

	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);

	struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);

	int ret;



	rctx->flags = tmpl->alg_flags;

	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;



	if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 &&

	    ctx->enc_keylen != AES_KEYSIZE_256) {

		ablkcipher_request_set_tfm(req, ctx->fallback);

		ret = encrypt ? crypto_ablkcipher_encrypt(req) :

				crypto_ablkcipher_decrypt(req);

		ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm));

		return ret;

	}



	return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);

}



static int qce_ablkcipher_encrypt(struct ablkcipher_request *req)

{

	return qce_ablkcipher_crypt(req, 1);

}



static int qce_ablkcipher_decrypt(struct ablkcipher_request *req)

{

	return qce_ablkcipher_crypt(req, 0);

}



static int qce_ablkcipher_init(struct crypto_tfm *tfm)

{

	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);



	memset(ctx, 0, sizeof(*ctx));

	tfm->crt_ablkcipher.reqsize = sizeof(struct qce_cipher_reqctx);



	ctx->fallback = crypto_alloc_ablkcipher(crypto_tfm_alg_name(tfm),

						CRYPTO_ALG_TYPE_ABLKCIPHER,

						CRYPTO_ALG_ASYNC |

						CRYPTO_ALG_NEED_FALLBACK);

	if (IS_ERR(ctx->fallback))

		return PTR_ERR(ctx->fallback);



	return 0;

}



static void qce_ablkcipher_exit(struct crypto_tfm *tfm)

{

	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);



	crypto_free_ablkcipher(ctx->fallback);

}



struct qce_ablkcipher_def {

	unsigned long flags;

	const char *name;

	const char *drv_name;

	unsigned int blocksize;

	unsigned int ivsize;

	unsigned int min_keysize;

	unsigned int max_keysize;

};



static const struct qce_ablkcipher_def ablkcipher_def[] = {

	{

		.flags		= QCE_ALG_AES | QCE_MODE_ECB,

		.name		= "ecb(aes)",

		.drv_name	= "ecb-aes-qce",

		.blocksize	= AES_BLOCK_SIZE,

		.ivsize		= AES_BLOCK_SIZE,

		.min_keysize	= AES_MIN_KEY_SIZE,

		.max_keysize	= AES_MAX_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_AES | QCE_MODE_CBC,

		.name		= "cbc(aes)",

		.drv_name	= "cbc-aes-qce",

		.blocksize	= AES_BLOCK_SIZE,

		.ivsize		= AES_BLOCK_SIZE,

		.min_keysize	= AES_MIN_KEY_SIZE,

		.max_keysize	= AES_MAX_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_AES | QCE_MODE_CTR,

		.name		= "ctr(aes)",

		.drv_name	= "ctr-aes-qce",

		.blocksize	= AES_BLOCK_SIZE,

		.ivsize		= AES_BLOCK_SIZE,

		.min_keysize	= AES_MIN_KEY_SIZE,

		.max_keysize	= AES_MAX_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_AES | QCE_MODE_XTS,

		.name		= "xts(aes)",

		.drv_name	= "xts-aes-qce",

		.blocksize	= AES_BLOCK_SIZE,

		.ivsize		= AES_BLOCK_SIZE,

		.min_keysize	= AES_MIN_KEY_SIZE,

		.max_keysize	= AES_MAX_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_DES | QCE_MODE_ECB,

		.name		= "ecb(des)",

		.drv_name	= "ecb-des-qce",

		.blocksize	= DES_BLOCK_SIZE,

		.ivsize		= 0,

		.min_keysize	= DES_KEY_SIZE,

		.max_keysize	= DES_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_DES | QCE_MODE_CBC,

		.name		= "cbc(des)",

		.drv_name	= "cbc-des-qce",

		.blocksize	= DES_BLOCK_SIZE,

		.ivsize		= DES_BLOCK_SIZE,

		.min_keysize	= DES_KEY_SIZE,

		.max_keysize	= DES_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_3DES | QCE_MODE_ECB,

		.name		= "ecb(des3_ede)",

		.drv_name	= "ecb-3des-qce",

		.blocksize	= DES3_EDE_BLOCK_SIZE,

		.ivsize		= 0,

		.min_keysize	= DES3_EDE_KEY_SIZE,

		.max_keysize	= DES3_EDE_KEY_SIZE,

	},

	{

		.flags		= QCE_ALG_3DES | QCE_MODE_CBC,

		.name		= "cbc(des3_ede)",

		.drv_name	= "cbc-3des-qce",

		.blocksize	= DES3_EDE_BLOCK_SIZE,

		.ivsize		= DES3_EDE_BLOCK_SIZE,

		.min_keysize	= DES3_EDE_KEY_SIZE,

		.max_keysize	= DES3_EDE_KEY_SIZE,

	},

};



static int qce_ablkcipher_register_one(const struct qce_ablkcipher_def *def,

				       struct qce_device *qce)

{

	struct qce_alg_template *tmpl;

	struct crypto_alg *alg;

	int ret;



	tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);

	if (!tmpl)

		return -ENOMEM;



	alg = &tmpl->alg.crypto;



	snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);

	snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",

		 def->drv_name);



	alg->cra_blocksize = def->blocksize;

	alg->cra_ablkcipher.ivsize = def->ivsize;

	alg->cra_ablkcipher.min_keysize = def->min_keysize;

	alg->cra_ablkcipher.max_keysize = def->max_keysize;

	alg->cra_ablkcipher.setkey = qce_ablkcipher_setkey;

	alg->cra_ablkcipher.encrypt = qce_ablkcipher_encrypt;

	alg->cra_ablkcipher.decrypt = qce_ablkcipher_decrypt;



	alg->cra_priority = 300;

	alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |

			 CRYPTO_ALG_NEED_FALLBACK;

	alg->cra_ctxsize = sizeof(struct qce_cipher_ctx);

	alg->cra_alignmask = 0;

	alg->cra_type = &crypto_ablkcipher_type;

	alg->cra_module = THIS_MODULE;

	alg->cra_init = qce_ablkcipher_init;

	alg->cra_exit = qce_ablkcipher_exit;

	INIT_LIST_HEAD(&alg->cra_list);



	INIT_LIST_HEAD(&tmpl->entry);

	tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_ABLKCIPHER;

	tmpl->alg_flags = def->flags;

	tmpl->qce = qce;



	ret = crypto_register_alg(alg);

	if (ret) {

		kfree(tmpl);

		dev_err(qce->dev, "%s registration failed\n", alg->cra_name);

		return ret;

	}



	list_add_tail(&tmpl->entry, &ablkcipher_algs);

	dev_dbg(qce->dev, "%s is registered\n", alg->cra_name);

	return 0;

}



static void qce_ablkcipher_unregister(struct qce_device *qce)

{

	struct qce_alg_template *tmpl, *n;



	list_for_each_entry_safe(tmpl, n, &ablkcipher_algs, entry) {

		crypto_unregister_alg(&tmpl->alg.crypto);

		list_del(&tmpl->entry);

		kfree(tmpl);

	}

}



static int qce_ablkcipher_register(struct qce_device *qce)

{

	int ret, i;



	for (i = 0; i < ARRAY_SIZE(ablkcipher_def); i++) {

		ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce);

		if (ret)

			goto err;

	}



	return 0;

err:

	qce_ablkcipher_unregister(qce);

	return ret;

}



const struct qce_algo_ops ablkcipher_ops = {

	.type = CRYPTO_ALG_TYPE_ABLKCIPHER,

	.register_algs = qce_ablkcipher_register,

	.unregister_algs = qce_ablkcipher_unregister,

	.async_req_handle = qce_ablkcipher_async_req_handle,

};

drivers/crypto/qce/cipher.h

0 → 100644
+68 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CIPHER_H_

#define _CIPHER_H_



#include "common.h"

#include "core.h"



#define QCE_MAX_KEY_SIZE	64



struct qce_cipher_ctx {

	u8 enc_key[QCE_MAX_KEY_SIZE];

	unsigned int enc_keylen;

	struct crypto_ablkcipher *fallback;

};



/**

 * struct qce_cipher_reqctx - holds private cipher objects per request

 * @flags: operation flags

 * @iv: pointer to the IV

 * @ivsize: IV size

 * @src_nents: source entries

 * @dst_nents: destination entries

 * @src_chained: is source chained

 * @dst_chained: is destination chained

 * @result_sg: scatterlist used for result buffer

 * @dst_tbl: destination sg table

 * @dst_sg: destination sg pointer table beginning

 * @src_tbl: source sg table

 * @src_sg: source sg pointer table beginning;

 * @cryptlen: crypto length

 */

struct qce_cipher_reqctx {

	unsigned long flags;

	u8 *iv;

	unsigned int ivsize;

	int src_nents;

	int dst_nents;

	bool src_chained;

	bool dst_chained;

	struct scatterlist result_sg;

	struct sg_table dst_tbl;

	struct scatterlist *dst_sg;

	struct sg_table src_tbl;

	struct scatterlist *src_sg;

	unsigned int cryptlen;

};



static inline struct qce_alg_template *to_cipher_tmpl(struct crypto_tfm *tfm)

{

	struct crypto_alg *alg = tfm->__crt_alg;

	return container_of(alg, struct qce_alg_template, alg.crypto);

}



extern const struct qce_algo_ops ablkcipher_ops;



#endif /* _CIPHER_H_ */

drivers/crypto/qce/common.c

0 → 100644
+435 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/crypto/qce/common.h

0 → 100644
+102 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _COMMON_H_

#define _COMMON_H_



#include <linux/crypto.h>

#include <linux/types.h>

#include <crypto/aes.h>

#include <crypto/hash.h>



/* key size in bytes */

#define QCE_SHA_HMAC_KEY_SIZE		64

#define QCE_MAX_CIPHER_KEY_SIZE		AES_KEYSIZE_256



/* IV length in bytes */

#define QCE_AES_IV_LENGTH		AES_BLOCK_SIZE

/* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */

#define QCE_MAX_IV_SIZE			AES_BLOCK_SIZE



/* maximum nonce bytes  */

#define QCE_MAX_NONCE			16

#define QCE_MAX_NONCE_WORDS		(QCE_MAX_NONCE / sizeof(u32))



/* burst size alignment requirement */

#define QCE_MAX_ALIGN_SIZE		64



/* cipher algorithms */

#define QCE_ALG_DES			BIT(0)

#define QCE_ALG_3DES			BIT(1)

#define QCE_ALG_AES			BIT(2)



/* hash and hmac algorithms */

#define QCE_HASH_SHA1			BIT(3)

#define QCE_HASH_SHA256			BIT(4)

#define QCE_HASH_SHA1_HMAC		BIT(5)

#define QCE_HASH_SHA256_HMAC		BIT(6)

#define QCE_HASH_AES_CMAC		BIT(7)



/* cipher modes */

#define QCE_MODE_CBC			BIT(8)

#define QCE_MODE_ECB			BIT(9)

#define QCE_MODE_CTR			BIT(10)

#define QCE_MODE_XTS			BIT(11)

#define QCE_MODE_CCM			BIT(12)

#define QCE_MODE_MASK			GENMASK(12, 8)



/* cipher encryption/decryption operations */

#define QCE_ENCRYPT			BIT(13)

#define QCE_DECRYPT			BIT(14)



#define IS_DES(flags)			(flags & QCE_ALG_DES)

#define IS_3DES(flags)			(flags & QCE_ALG_3DES)

#define IS_AES(flags)			(flags & QCE_ALG_AES)



#define IS_SHA1(flags)			(flags & QCE_HASH_SHA1)

#define IS_SHA256(flags)		(flags & QCE_HASH_SHA256)

#define IS_SHA1_HMAC(flags)		(flags & QCE_HASH_SHA1_HMAC)

#define IS_SHA256_HMAC(flags)		(flags & QCE_HASH_SHA256_HMAC)

#define IS_CMAC(flags)			(flags & QCE_HASH_AES_CMAC)

#define IS_SHA(flags)			(IS_SHA1(flags) || IS_SHA256(flags))

#define IS_SHA_HMAC(flags)		\

		(IS_SHA1_HMAC(flags) || IS_SHA256_HMAC(flags))



#define IS_CBC(mode)			(mode & QCE_MODE_CBC)

#define IS_ECB(mode)			(mode & QCE_MODE_ECB)

#define IS_CTR(mode)			(mode & QCE_MODE_CTR)

#define IS_XTS(mode)			(mode & QCE_MODE_XTS)

#define IS_CCM(mode)			(mode & QCE_MODE_CCM)



#define IS_ENCRYPT(dir)			(dir & QCE_ENCRYPT)

#define IS_DECRYPT(dir)			(dir & QCE_DECRYPT)



struct qce_alg_template {

	struct list_head entry;

	u32 crypto_alg_type;

	unsigned long alg_flags;

	const __be32 *std_iv;

	union {

		struct crypto_alg crypto;

		struct ahash_alg ahash;

	} alg;

	struct qce_device *qce;

};



void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);

int qce_check_status(struct qce_device *qce, u32 *status);

void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);

int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,

	      u32 offset);



#endif /* _COMMON_H_ */

drivers/crypto/qce/core.c

0 → 100644
+286 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk.h>

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/spinlock.h>

#include <linux/types.h>

#include <crypto/algapi.h>

#include <crypto/internal/hash.h>

#include <crypto/sha.h>



#include "core.h"

#include "cipher.h"

#include "sha.h"



#define QCE_MAJOR_VERSION5	0x05

#define QCE_QUEUE_LENGTH	1



static const struct qce_algo_ops *qce_ops[] = {

	&ablkcipher_ops,

	&ahash_ops,

};



static void qce_unregister_algs(struct qce_device *qce)

{

	const struct qce_algo_ops *ops;

	int i;



	for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {

		ops = qce_ops[i];

		ops->unregister_algs(qce);

	}

}



static int qce_register_algs(struct qce_device *qce)

{

	const struct qce_algo_ops *ops;

	int i, ret = -ENODEV;



	for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {

		ops = qce_ops[i];

		ret = ops->register_algs(qce);

		if (ret)

			break;

	}



	return ret;

}



static int qce_handle_request(struct crypto_async_request *async_req)

{

	int ret = -EINVAL, i;

	const struct qce_algo_ops *ops;

	u32 type = crypto_tfm_alg_type(async_req->tfm);



	for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {

		ops = qce_ops[i];

		if (type != ops->type)

			continue;

		ret = ops->async_req_handle(async_req);

		break;

	}



	return ret;

}



static int qce_handle_queue(struct qce_device *qce,

			    struct crypto_async_request *req)

{

	struct crypto_async_request *async_req, *backlog;

	unsigned long flags;

	int ret = 0, err;



	spin_lock_irqsave(&qce->lock, flags);



	if (req)

		ret = crypto_enqueue_request(&qce->queue, req);



	/* busy, do not dequeue request */

	if (qce->req) {

		spin_unlock_irqrestore(&qce->lock, flags);

		return ret;

	}



	backlog = crypto_get_backlog(&qce->queue);

	async_req = crypto_dequeue_request(&qce->queue);

	if (async_req)

		qce->req = async_req;



	spin_unlock_irqrestore(&qce->lock, flags);



	if (!async_req)

		return ret;



	if (backlog) {

		spin_lock_bh(&qce->lock);

		backlog->complete(backlog, -EINPROGRESS);

		spin_unlock_bh(&qce->lock);

	}



	err = qce_handle_request(async_req);

	if (err) {

		qce->result = err;

		tasklet_schedule(&qce->done_tasklet);

	}



	return ret;

}



static void qce_tasklet_req_done(unsigned long data)

{

	struct qce_device *qce = (struct qce_device *)data;

	struct crypto_async_request *req;

	unsigned long flags;



	spin_lock_irqsave(&qce->lock, flags);

	req = qce->req;

	qce->req = NULL;

	spin_unlock_irqrestore(&qce->lock, flags);



	if (req)

		req->complete(req, qce->result);



	qce_handle_queue(qce, NULL);

}



static int qce_async_request_enqueue(struct qce_device *qce,

				     struct crypto_async_request *req)

{

	return qce_handle_queue(qce, req);

}



static void qce_async_request_done(struct qce_device *qce, int ret)

{

	qce->result = ret;

	tasklet_schedule(&qce->done_tasklet);

}



static int qce_check_version(struct qce_device *qce)

{

	u32 major, minor, step;



	qce_get_version(qce, &major, &minor, &step);



	/*

	 * the driver does not support v5 with minor 0 because it has special

	 * alignment requirements.

	 */

	if (major != QCE_MAJOR_VERSION5 || minor == 0)

		return -ENODEV;



	qce->burst_size = QCE_BAM_BURST_SIZE;

	qce->pipe_pair_id = 1;



	dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",

		major, minor, step);



	return 0;

}



static int qce_crypto_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct qce_device *qce;

	struct resource *res;

	int ret;



	qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);

	if (!qce)

		return -ENOMEM;



	qce->dev = dev;

	platform_set_drvdata(pdev, qce);



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	qce->base = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(qce->base))

		return PTR_ERR(qce->base);



	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));

	if (ret < 0)

		return ret;



	qce->core = devm_clk_get(qce->dev, "core");

	if (IS_ERR(qce->core))

		return PTR_ERR(qce->core);



	qce->iface = devm_clk_get(qce->dev, "iface");

	if (IS_ERR(qce->iface))

		return PTR_ERR(qce->iface);



	qce->bus = devm_clk_get(qce->dev, "bus");

	if (IS_ERR(qce->bus))

		return PTR_ERR(qce->bus);



	ret = clk_prepare_enable(qce->core);

	if (ret)

		return ret;



	ret = clk_prepare_enable(qce->iface);

	if (ret)

		goto err_clks_core;



	ret = clk_prepare_enable(qce->bus);

	if (ret)

		goto err_clks_iface;



	ret = qce_dma_request(qce->dev, &qce->dma);

	if (ret)

		goto err_clks;



	ret = qce_check_version(qce);

	if (ret)

		goto err_clks;



	spin_lock_init(&qce->lock);

	tasklet_init(&qce->done_tasklet, qce_tasklet_req_done,

		     (unsigned long)qce);

	crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);



	qce->async_req_enqueue = qce_async_request_enqueue;

	qce->async_req_done = qce_async_request_done;



	ret = qce_register_algs(qce);

	if (ret)

		goto err_dma;



	return 0;



err_dma:

	qce_dma_release(&qce->dma);

err_clks:

	clk_disable_unprepare(qce->bus);

err_clks_iface:

	clk_disable_unprepare(qce->iface);

err_clks_core:

	clk_disable_unprepare(qce->core);

	return ret;

}



static int qce_crypto_remove(struct platform_device *pdev)

{

	struct qce_device *qce = platform_get_drvdata(pdev);



	tasklet_kill(&qce->done_tasklet);

	qce_unregister_algs(qce);

	qce_dma_release(&qce->dma);

	clk_disable_unprepare(qce->bus);

	clk_disable_unprepare(qce->iface);

	clk_disable_unprepare(qce->core);

	return 0;

}



static const struct of_device_id qce_crypto_of_match[] = {

	{ .compatible = "qcom,crypto-v5.1", },

	{}

};

MODULE_DEVICE_TABLE(of, qce_crypto_of_match);



static struct platform_driver qce_crypto_driver = {

	.probe = qce_crypto_probe,

	.remove = qce_crypto_remove,

	.driver = {

		.owner = THIS_MODULE,

		.name = KBUILD_MODNAME,

		.of_match_table = qce_crypto_of_match,

	},

};

module_platform_driver(qce_crypto_driver);



MODULE_LICENSE("GPL v2");

MODULE_DESCRIPTION("Qualcomm crypto engine driver");

MODULE_ALIAS("platform:" KBUILD_MODNAME);

MODULE_AUTHOR("The Linux Foundation");