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Commit eb6008ad authored by Rafael Barbalho's avatar Rafael Barbalho Committed by Daniel Vetter
Browse files

drm/i915: Fix framecount offset 



The framecount register was still using the old PIPE macro instead
of the new PIPE2 macro

Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0d95e11b

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -3622,9 +3622,9 @@ enum punit_power_well { 
#define   PIPE_PIXEL_MASK         0x00ffffff

#define   PIPE_PIXEL_SHIFT        0

/* GM45+ just has to be different */

#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70040)

#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70044)

#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)

#define _PIPEA_FRMCOUNT_GM45	0x70040

#define _PIPEA_FLIPCOUNT_GM45	0x70044

#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)



/* Cursor A & B regs */

#define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)