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Commit e9ebb68b authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50: support fractional feedback divider on newer chips 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 7e99a9b2

drivers/gpu/drm/nouveau/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nv50_cursor.o nv50_display.o nv50_fbcon.o \

             nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \

             nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \

             nv17_gpio.o nv50_gpio.o

             nv17_gpio.o nv50_gpio.o \

	     nv50_calc.o



nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o

nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

drivers/gpu/drm/nouveau/nouveau_drv.h

+6 −0
Original line number Diff line number Diff line
@@ -1170,6 +1170,12 @@ int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 
int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);

int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);



/* nv50_calc. */

int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,

		  int *N1, int *M1, int *N2, int *M2, int *P);

int nv50_calc_pll2(struct drm_device *, struct pll_lims *,

		   int clk, int *N, int *fN, int *M, int *P);



#ifndef ioread32_native

#ifdef __BIG_ENDIAN

#define ioread16_native ioread16be

drivers/gpu/drm/nouveau/nv50_calc.c

0 → 100644
+87 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */



#include "drmP.h"

#include "drm_fixed.h"

#include "nouveau_drv.h"

#include "nouveau_hw.h"



int

nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk,

	      int *N1, int *M1, int *N2, int *M2, int *P)

{

	struct nouveau_pll_vals pll_vals;

	int ret;



	ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals);

	if (ret <= 0)

		return ret;



	*N1 = pll_vals.N1;

	*M1 = pll_vals.M1;

	*N2 = pll_vals.N2;

	*M2 = pll_vals.M2;

	*P = pll_vals.log2P;

	return ret;

}



int

nv50_calc_pll2(struct drm_device *dev, struct pll_lims *pll, int clk,

	       int *N, int *fN, int *M, int *P)

{

	fixed20_12 fb_div, a, b;



	*P = pll->vco1.maxfreq / clk;

	if (*P > pll->max_p)

		*P = pll->max_p;

	if (*P < pll->min_p)

		*P = pll->min_p;



	/* *M = ceil(refclk / pll->vco.max_inputfreq); */

	a.full = dfixed_const(pll->refclk);

	b.full = dfixed_const(pll->vco1.max_inputfreq);

	a.full = dfixed_div(a, b);

	a.full = dfixed_ceil(a);

	*M = dfixed_trunc(a);



	/* fb_div = (vco * *M) / refclk; */

	fb_div.full = dfixed_const(clk * *P);

	fb_div.full = dfixed_mul(fb_div, a);

	a.full = dfixed_const(pll->refclk);

	fb_div.full = dfixed_div(fb_div, a);



	/* *N = floor(fb_div); */

	a.full = dfixed_floor(fb_div);

	*N = dfixed_trunc(fb_div);



	/* *fN = (fmod(fb_div, 1.0) * 8192) - 4096; */

	b.full = dfixed_const(8192);

	a.full = dfixed_mul(a, b);

	fb_div.full = dfixed_mul(fb_div, b);

	fb_div.full = fb_div.full - a.full;

	*fN = dfixed_trunc(fb_div) - 4096;

	*fN &= 0xffff;



	return clk;

}

drivers/gpu/drm/nouveau/nv50_crtc.c

+25 −23
Original line number Diff line number Diff line
@@ -264,38 +264,40 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update) 
int

nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)

{

	uint32_t pll_reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);

	struct nouveau_pll_vals pll;

	struct pll_lims limits;

	uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);

	struct pll_lims pll;

	uint32_t reg1, reg2;

	int ret;

	int ret, N1, M1, N2, M2, P;



	ret = get_pll_limits(dev, pll_reg, &limits);

	ret = get_pll_limits(dev, reg, &pll);

	if (ret)

		return ret;



	ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll);

	if (pll.vco2.maxfreq) {

		ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);

		if (ret <= 0)

		return ret;

			return 0;



	if (limits.vco2.maxfreq) {

		NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",

			 pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P);



		reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;

		reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;

		nv_wr32(dev, pll_reg, 0x10000611);

		nv_wr32(dev, pll_reg + 4, reg1 | (pll.M1 << 16) | pll.N1);

		nv_wr32(dev, pll_reg + 8,

			reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);

			 pclk, ret, N1, M1, N2, M2, P);



		reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00;

		reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00;

		nv_wr32(dev, reg, 0x10000611);

		nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);

		nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);

	} else {

		NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n",

			 pclk, ret, pll.N1, pll.M1, pll.log2P);

		ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);

		if (ret <= 0)

			return 0;



		NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",

			 pclk, ret, N1, N2, M1, P);



		reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;

		nv_wr32(dev, pll_reg, 0x50000610);

		nv_wr32(dev, pll_reg + 4, reg1 |

			(pll.log2P << 16) | (pll.M1 << 8) | pll.N1);

		reg1 = nv_rd32(dev, reg + 4) & 0xffc00000;

		nv_wr32(dev, reg, 0x50000610);

		nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);

		nv_wr32(dev, reg + 8, N2);

	}



	return 0;