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Commit e9c33572 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Ralf Baechle
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[MIPS] Use real cache invalidate 



R10k non coherent machines need a real dma cache invalidate to get rid of
speculative stores in cache.  For other machines this promises a slight
speedup.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 87353d8a

arch/mips/mm/c-r4k.c

+2 −2
Original line number Diff line number Diff line
@@ -589,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 
		if (size >= scache_size)

			r4k_blast_scache();

		else

			blast_scache_range(addr, addr + size);

			blast_inv_scache_range(addr, addr + size);

		return;

	}
@@ -597,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 
		r4k_blast_dcache();

	} else {

		R4600_HIT_CACHEOP_WAR_IMPL;

		blast_dcache_range(addr, addr + size);

		blast_inv_dcache_range(addr, addr + size);

	}



	bc_inv(addr, size);

include/asm-mips/r4kcache.h

+7 −0
Original line number Diff line number Diff line
@@ -403,6 +403,13 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) 
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)



__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)

__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)

__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)



/* build blast_xxx_range, protected_blast_xxx_range */

#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \

static inline void prot##blast_##pfx##cache##_range(unsigned long start, \