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Commit e9a321c6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: fix DAC interrupt handling on DCE5+ 



DCE5 and newer hardware only has 1 DAC.  Use the correct
offset.  This may fix display problems on certain board
configurations.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 50efa51a

drivers/gpu/drm/radeon/evergreen.c

+2 −2
Original line number Diff line number Diff line
@@ -4348,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	/* only one DAC on DCE6 */

	if (!ASIC_IS_DCE6(rdev))

	/* only one DAC on DCE5 */

	if (!ASIC_IS_DCE5(rdev))

		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

	WREG32(DACB_AUTODETECT_INT_CONTROL, 0);

drivers/gpu/drm/radeon/si.c

+1 −1
Original line number Diff line number Diff line
@@ -5682,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) 
	}



	if (!ASIC_IS_NODCE(rdev)) {

		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

		WREG32(DAC_AUTODETECT_INT_CONTROL, 0);



		tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;

		WREG32(DC_HPD1_INT_CONTROL, tmp);

drivers/gpu/drm/radeon/sid.h

+1 −1
Original line number Diff line number Diff line
@@ -822,7 +822,7 @@ 
#       define GRPH_PFLIP_INT_MASK                      (1 << 0)

#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)



#define	DACA_AUTODETECT_INT_CONTROL			0x66c8

#define	DAC_AUTODETECT_INT_CONTROL			0x67c8



#define DC_HPD1_INT_STATUS                              0x601c

#define DC_HPD2_INT_STATUS                              0x6028