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Commit e98ff0f5 authored by Russell King's avatar Russell King
Browse files

ARM: smp_on_up: allow non-ARM SMP processors 



Allow non-ARM SMP processors to use the SMP_ON_UP feature.  CPUs
supporting SMP must have the new CPU ID format, so check for this first.
Then check for ARM11MPCore, which fails the MPIDR check.  Lastly check
the MPIDR reports multiprocessing extensions and that the CPU is part of
a multiprocessing system.

Cc: <stable@kernel.org>
Reported-and-Tested-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c1928022

arch/arm/kernel/head.S

+10 −12
Original line number Diff line number Diff line
@@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on) 


#ifdef CONFIG_SMP_ON_UP

__fixup_smp:

	mov	r4, #0x00070000

	orr	r3, r4, #0xff000000	@ mask 0xff070000

	orr	r4, r4, #0x41000000	@ val 0x41070000

	and	r0, r9, r3

	teq	r0, r4			@ ARM CPU and ARMv6/v7?

	and	r3, r9, #0x000f0000	@ architecture version

	teq	r3, #0x000f0000		@ CPU ID supported?

	bne	__fixup_smp_on_up	@ no, assume UP



	orr	r3, r3, #0x0000ff00

	orr	r3, r3, #0x000000f0	@ mask 0xff07fff0

	bic	r3, r9, #0x00ff0000

	bic	r3, r3, #0x0000000f	@ mask 0xff00fff0

	mov	r4, #0x41000000

	orr	r4, r4, #0x0000b000

	orr	r4, r4, #0x00000020	@ val 0x4107b020

	and	r0, r9, r3

	teq	r0, r4			@ ARM 11MPCore?

	orr	r4, r4, #0x00000020	@ val 0x4100b020

	teq	r3, r4			@ ARM 11MPCore?

	moveq	pc, lr			@ yes, assume SMP



	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR

	tst	r0, #1 << 31

	movne	pc, lr			@ bit 31 => SMP

	and	r0, r0, #0xc0000000	@ multiprocessing extensions and

	teq	r0, #0x80000000		@ not part of a uniprocessor system?

	moveq	pc, lr			@ yes, assume SMP



__fixup_smp_on_up:

	adr	r0, 1f