Loading arch/arm/mach-s3c6400/include/mach/map.h +3 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,9 @@ #define S3C64XX_PA_VIC0 (0x71200000) #define S3C64XX_PA_VIC1 (0x71300000) #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) Loading arch/arm/plat-s3c64xx/cpu.c +5 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,11 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C64XX_VA_MODEM, .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), .length = SZ_4K, .type = MT_DEVICE, }, }; Loading arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h 0 → 100644 +25 −0 Original line number Diff line number Diff line /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * * S3C64XX - GPIO memory port register definitions */ #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H #define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */ arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +169 −17 Original line number Diff line number Diff line Loading @@ -13,23 +13,175 @@ /* Base addresses for each of the banks */ #define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) #define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) #define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) #define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) #define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) #define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) #define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) #define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) #define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) #define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) #define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) #define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) #define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) #define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) #define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) #define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) #define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) /* SPCON */ #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) #define S3C64XX_SPCON_USBH_DMPD (1 << 7) #define S3C64XX_SPCON_USBH_DPPD (1 << 6) #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) /* External interrupt registers */ #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) /* GPIO sleep configuration */ #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) #define S3C64XX_SLPEN_USE_xSLP (1 << 0) #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ arch/arm/plat-s3c64xx/include/plat/regs-modem.h 0 → 100644 +31 −0 Original line number Diff line number Diff line /* arch/arm/plat-s3c64xx/include/plat/regs-modem.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * * S3C64XX - modem block registers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __PLAT_S3C64XX_REGS_MODEM_H #define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ #define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) #define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) #define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) #define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8) #define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC) #define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10) #define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14) #define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18) #define MIFPCON_INT2M_LEVEL (1 << 4) #define MIFPCON_LCD_BYPASS (1 << 3) #endif /* __PLAT_S3C64XX_REGS_MODEM_H */ Loading
arch/arm/mach-s3c6400/include/mach/map.h +3 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,9 @@ #define S3C64XX_PA_VIC0 (0x71200000) #define S3C64XX_PA_VIC1 (0x71300000) #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) Loading
arch/arm/plat-s3c64xx/cpu.c +5 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,11 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C64XX_VA_MODEM, .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), .length = SZ_4K, .type = MT_DEVICE, }, }; Loading
arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h 0 → 100644 +25 −0 Original line number Diff line number Diff line /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * * S3C64XX - GPIO memory port register definitions */ #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H #define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +169 −17 Original line number Diff line number Diff line Loading @@ -13,23 +13,175 @@ /* Base addresses for each of the banks */ #define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) #define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) #define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) #define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) #define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) #define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) #define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) #define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) #define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) #define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) #define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) #define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) #define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) #define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) #define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) #define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) #define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) /* SPCON */ #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) #define S3C64XX_SPCON_USBH_DMPD (1 << 7) #define S3C64XX_SPCON_USBH_DPPD (1 << 6) #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) /* External interrupt registers */ #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) /* GPIO sleep configuration */ #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) #define S3C64XX_SLPEN_USE_xSLP (1 << 0) #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
arch/arm/plat-s3c64xx/include/plat/regs-modem.h 0 → 100644 +31 −0 Original line number Diff line number Diff line /* arch/arm/plat-s3c64xx/include/plat/regs-modem.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * * S3C64XX - modem block registers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __PLAT_S3C64XX_REGS_MODEM_H #define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ #define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) #define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) #define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) #define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8) #define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC) #define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10) #define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14) #define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18) #define MIFPCON_INT2M_LEVEL (1 << 4) #define MIFPCON_LCD_BYPASS (1 << 3) #endif /* __PLAT_S3C64XX_REGS_MODEM_H */
