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Commit e80f14b6 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Don't save/restore RS when not used 



v2: fix conflict on rebase.

Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 98a2e5f9

drivers/gpu/drm/i915/i915_gem_context.c

+6 −4
Original line number Diff line number Diff line
@@ -458,6 +458,7 @@ mi_set_context(struct intel_engine_cs *ring, 
	       struct intel_context *new_context,

	       u32 hw_flags)

{

	u32 flags = hw_flags | MI_MM_SPACE_GTT;

	int ret;



	/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
@@ -471,6 +472,10 @@ mi_set_context(struct intel_engine_cs *ring, 
			return ret;

	}



	/* These flags are for resource streamer on HSW+ */

	if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)

		flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);



	ret = intel_ring_begin(ring, 6);

	if (ret)

		return ret;
@@ -484,10 +489,7 @@ mi_set_context(struct intel_engine_cs *ring, 
	intel_ring_emit(ring, MI_NOOP);

	intel_ring_emit(ring, MI_SET_CONTEXT);

	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) |

			MI_MM_SPACE_GTT |

			MI_SAVE_EXT_STATE_EN |

			MI_RESTORE_EXT_STATE_EN |

			hw_flags);

			flags);

	/*

	 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP

	 * WaMiSetContext_Hang:snb,ivb,vlv