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Commit e7472422 authored by Victoria Milhoan's avatar Victoria Milhoan Committed by Herbert Xu
Browse files

crypto: caam - Add cache coherency support 



Freescale i.MX6 ARM platforms do not support hardware cache coherency.
This patch adds cache coherency support to the CAAM driver.

Signed-off-by: default avatarVictoria Milhoan <vicki.milhoan@freescale.com>
Tested-by: default avatarHoria Geantă <horia.geanta@freescale.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent bf20d772

drivers/crypto/caam/caamhash.c

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ struct caam_hash_state { 
	int buflen_0;

	u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;

	int buflen_1;

	u8 caam_ctx[MAX_CTX_LEN];

	u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;

	int (*update)(struct ahash_request *req);

	int (*final)(struct ahash_request *req);

	int (*finup)(struct ahash_request *req);

drivers/crypto/caam/caamrng.c

+4 −0
Original line number Diff line number Diff line
@@ -108,6 +108,10 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 err, void *context) 


	atomic_set(&bd->empty, BUF_NOT_EMPTY);

	complete(&bd->filled);



	/* Buffer refilled, invalidate cache */

	dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);



#ifdef DEBUG

	print_hex_dump(KERN_ERR, "rng refreshed buf@: ",

		       DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1);

drivers/crypto/caam/jr.c

+18 −0
Original line number Diff line number Diff line
@@ -202,6 +202,13 @@ static void caam_jr_dequeue(unsigned long devarg) 
		userdesc = jrp->entinfo[sw_idx].desc_addr_virt;

		userstatus = jrp->outring[hw_idx].jrstatus;



		/*

		 * Make sure all information from the job has been obtained

		 * before telling CAAM that the job has been removed from the

		 * output ring.

		 */

		mb();



		/* set done */

		wr_reg32(&jrp->rregs->outring_rmvd, 1);
@@ -351,12 +358,23 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, 


	jrp->inpring[jrp->inp_ring_write_index] = desc_dma;



	/*

	 * Guarantee that the descriptor's DMA address has been written to

	 * the next slot in the ring before the write index is updated, since

	 * other cores may update this index independently.

	 */

	smp_wmb();



	jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &

				    (JOBR_DEPTH - 1);

	jrp->head = (head + 1) & (JOBR_DEPTH - 1);



	/*

	 * Ensure that all job information has been written before

	 * notifying CAAM that a new job was added to the input ring.

	 */

	wmb();



	wr_reg32(&jrp->rregs->inpring_jobadd, 1);



	spin_unlock_bh(&jrp->inplock);