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Commit e666d66b authored by Michel Dänzer's avatar Michel Dänzer Committed by Dave Airlie
Browse files

vmwgfx: Don't write to read-only registers 



Signed-off-by: default avatarMichel Dänzer <daenzer@vmware.com>
Signed-off-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f01b7ba0

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

+0 −5
Original line number Diff line number Diff line
@@ -195,12 +195,7 @@ struct vmw_private { 
	struct vmw_vga_topology_state vga_save[VMWGFX_MAX_DISPLAYS];

	uint32_t vga_width;

	uint32_t vga_height;

	uint32_t vga_depth;

	uint32_t vga_bpp;

	uint32_t vga_pseudo;

	uint32_t vga_red_mask;

	uint32_t vga_green_mask;

	uint32_t vga_blue_mask;

	uint32_t vga_bpl;

	uint32_t vga_pitchlock;

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

+0 −14
Original line number Diff line number Diff line
@@ -1001,10 +1001,6 @@ void vmw_kms_write_svga(struct vmw_private *vmw_priv, 
	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);

	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);

	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bbp);

	vmw_write(vmw_priv, SVGA_REG_DEPTH, depth);

	vmw_write(vmw_priv, SVGA_REG_RED_MASK, 0x00ff0000);

	vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);

	vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, 0x000000ff);

}



int vmw_kms_save_vga(struct vmw_private *vmw_priv)
@@ -1014,12 +1010,7 @@ int vmw_kms_save_vga(struct vmw_private *vmw_priv) 


	vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);

	vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);

	vmw_priv->vga_depth = vmw_read(vmw_priv, SVGA_REG_DEPTH);

	vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);

	vmw_priv->vga_pseudo = vmw_read(vmw_priv, SVGA_REG_PSEUDOCOLOR);

	vmw_priv->vga_red_mask = vmw_read(vmw_priv, SVGA_REG_RED_MASK);

	vmw_priv->vga_blue_mask = vmw_read(vmw_priv, SVGA_REG_BLUE_MASK);

	vmw_priv->vga_green_mask = vmw_read(vmw_priv, SVGA_REG_GREEN_MASK);

	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)

		vmw_priv->vga_pitchlock =

		  vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
@@ -1068,12 +1059,7 @@ int vmw_kms_restore_vga(struct vmw_private *vmw_priv) 


	vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);

	vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);

	vmw_write(vmw_priv, SVGA_REG_DEPTH, vmw_priv->vga_depth);

	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);

	vmw_write(vmw_priv, SVGA_REG_PSEUDOCOLOR, vmw_priv->vga_pseudo);

	vmw_write(vmw_priv, SVGA_REG_RED_MASK, vmw_priv->vga_red_mask);

	vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, vmw_priv->vga_green_mask);

	vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, vmw_priv->vga_blue_mask);

	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)

		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,

			  vmw_priv->vga_pitchlock);