Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e5674ad6 authored by Tony Wu's avatar Tony Wu Committed by Ralf Baechle
Browse files

MIPS: Separate two consecutive loads in memset.S 



partial_fixup is used in noreorder block.

Separating two consecutive loads can save one cycle on processors with
GPR intrelock and can fix load-use on processors that need a load delay slot.

Also do so for fwd_fixup.

[Ralf: Only R2000/R3000 class processors are lacking the the load-user
interlock and even some of those got it retrofitted.  With R2000/R3000
being fairly uncommon these days the impact of this bug should be minor.]

Signed-off-by: default avatarTony Wu <tung7970@gmail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1768/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 515b029d

arch/mips/lib/memset.S

+2 −2
Original line number Diff line number Diff line
@@ -161,16 +161,16 @@ FEXPORT(__bzero) 


.Lfwd_fixup:

	PTR_L		t0, TI_TASK($28)

	LONG_L		t0, THREAD_BUADDR(t0)

	andi		a2, 0x3f

	LONG_L		t0, THREAD_BUADDR(t0)

	LONG_ADDU	a2, t1

	jr		ra

	 LONG_SUBU	a2, t0



.Lpartial_fixup:

	PTR_L		t0, TI_TASK($28)

	LONG_L		t0, THREAD_BUADDR(t0)

	andi		a2, LONGMASK

	LONG_L		t0, THREAD_BUADDR(t0)

	LONG_ADDU	a2, t1

	jr		ra

	 LONG_SUBU	a2, t0