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Commit e55174e9 authored by Michael Neuling's avatar Michael Neuling Committed by Benjamin Herrenschmidt
Browse files

powerpc: Fixes for instructions not using correct register naming 



These macros are using integers where they could be using logical
names since they take registers.

We are going to enforce this soon, so fix these up now.

Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 03a22bfc

arch/powerpc/kernel/exceptions-64e.S

+4 −4
Original line number Diff line number Diff line
@@ -903,7 +903,7 @@ skpinv: addi r6,r6,1 /* Increment */ 
	bne	1b				/* If not, repeat */



	/* Invalidate all TLBs */

	PPC_TLBILX_ALL(0,0)

	PPC_TLBILX_ALL(R0,R0)

	sync

	isync
@@ -961,7 +961,7 @@ skpinv: addi r6,r6,1 /* Increment */ 
	tlbwe



	/* Invalidate TLB1 */

	PPC_TLBILX_ALL(0,0)

	PPC_TLBILX_ALL(R0,R0)

	sync

	isync
@@ -1020,7 +1020,7 @@ skpinv: addi r6,r6,1 /* Increment */ 
	tlbwe



	/* Invalidate TLB1 */

	PPC_TLBILX_ALL(0,0)

	PPC_TLBILX_ALL(R0,R0)

	sync

	isync
@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush: 
	tlbwe

#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */



	PPC_TLBILX(0,0,0)

	PPC_TLBILX(0,R0,R0)

	sync

	isync

arch/powerpc/kernel/misc_64.S

+2 −2
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ _GLOBAL(real_205_readb) 
	mtmsrd	r0

	sync

	isync

	LBZCIX(R3,0,R3)

	LBZCIX(R3,R0,R3)

	isync

	mtmsrd	r7

	sync
@@ -324,7 +324,7 @@ _GLOBAL(real_205_writeb) 
	mtmsrd	r0

	sync

	isync

	STBCIX(R3,0,R4)

	STBCIX(R3,R0,R4)

	isync

	mtmsrd	r7

	sync

arch/powerpc/lib/ldstfp.S

+2 −2
Original line number Diff line number Diff line
@@ -332,7 +332,7 @@ _GLOBAL(do_lxvd2x) 
	beq	cr7,1f

	STXVD2X(0,R1,R8)

1:	li	r9,-EFAULT

2:	LXVD2X(0,0,R4)

2:	LXVD2X(0,R0,R4)

	li	r9,0

3:	beq	cr7,4f

	bl	put_vsr
@@ -361,7 +361,7 @@ _GLOBAL(do_stxvd2x) 
	STXVD2X(0,R1,R8)

	bl	get_vsr

1:	li	r9,-EFAULT

2:	STXVD2X(0,0,R4)

2:	STXVD2X(0,R0,R4)

	li	r9,0

3:	beq	cr7,4f

	LXVD2X(0,R1,R8)

arch/powerpc/mm/tlb_nohash_low.S

+5 −5
Original line number Diff line number Diff line
@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION 
	andi.	r3,r3,MMUCSR0_TLBFI@l

	bne	1b

MMU_FTR_SECTION_ELSE

	PPC_TLBILX_ALL(0,0)

	PPC_TLBILX_ALL(R0,R0)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)

	msync

	isync
@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION 
	wrteei	0

	mfspr	r4,SPRN_MAS6	/* save MAS6 */

	mtspr	SPRN_MAS6,r3

	PPC_TLBILX_PID(0,0)

	PPC_TLBILX_PID(R0,R0)

	mtspr	SPRN_MAS6,r4	/* restore MAS6 */

	wrtee	r10

MMU_FTR_SECTION_ELSE
@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid) 
	mfmsr	r10

	wrteei	0

	mtspr	SPRN_MAS6,r4

	PPC_TLBILX_PID(0,0)

	PPC_TLBILX_PID(R0,R0)

	wrtee	r10

	msync

	isync
@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind) 
	ori	r4,r4,MAS6_SIND

	wrteei	0

	mtspr	SPRN_MAS6,r4

	PPC_TLBILX_PID(0,0)

	PPC_TLBILX_PID(R0,R0)

	wrtee	r10

	msync

	isync

	blr



_GLOBAL(_tlbil_all)

	PPC_TLBILX_ALL(0,0)

	PPC_TLBILX_ALL(R0,R0)

	msync

	isync

	blr