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Commit e4ffd173 authored by Chris Wilson's avatar Chris Wilson Committed by Keith Packard
Browse files

drm/i915: Add an interface to dynamically change the cache level 



[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]

[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d5bd1449

drivers/gpu/drm/i915/i915_drv.h

+5 −0
Original line number Diff line number Diff line
@@ -1223,9 +1223,14 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file); 
uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);



int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

				    enum i915_cache_level cache_level);



/* i915_gem_gtt.c */

void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);

void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,

				enum i915_cache_level cache_level);

void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);



/* i915_gem_evict.c */

drivers/gpu/drm/i915/i915_gem.c

+60 −0
Original line number Diff line number Diff line
@@ -3034,6 +3034,66 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
	return 0;

}



int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

				    enum i915_cache_level cache_level)

{

	int ret;



	if (obj->cache_level == cache_level)

		return 0;



	if (obj->pin_count) {

		DRM_DEBUG("can not change the cache level of pinned objects\n");

		return -EBUSY;

	}



	if (obj->gtt_space) {

		ret = i915_gem_object_finish_gpu(obj);

		if (ret)

			return ret;



		i915_gem_object_finish_gtt(obj);



		/* Before SandyBridge, you could not use tiling or fence

		 * registers with snooped memory, so relinquish any fences

		 * currently pointing to our region in the aperture.

		 */

		if (INTEL_INFO(obj->base.dev)->gen < 6) {

			ret = i915_gem_object_put_fence(obj);

			if (ret)

				return ret;

		}



		i915_gem_gtt_rebind_object(obj, cache_level);

	}



	if (cache_level == I915_CACHE_NONE) {

		u32 old_read_domains, old_write_domain;



		/* If we're coming from LLC cached, then we haven't

		 * actually been tracking whether the data is in the

		 * CPU cache or not, since we only allow one bit set

		 * in obj->write_domain and have been skipping the clflushes.

		 * Just set it to the CPU cache for now.

		 */

		WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);

		WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);



		old_read_domains = obj->base.read_domains;

		old_write_domain = obj->base.write_domain;



		obj->base.read_domains = I915_GEM_DOMAIN_CPU;

		obj->base.write_domain = I915_GEM_DOMAIN_CPU;



		trace_i915_gem_object_change_domain(obj,

						    old_read_domains,

						    old_write_domain);

	}



	obj->cache_level = cache_level;

	return 0;

}



/*

 * Prepare buffer for display plane. Use uninterruptible for possible flush

 * wait, as in modesetting process we're not supposed to be interrupted.

drivers/gpu/drm/i915/i915_gem_gtt.c

+2 −5
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ 
#include "i915_trace.h"

#include "intel_drv.h"



static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,

				       enum i915_cache_level cache_level);



/* XXX kill agp_type! */

static unsigned int cache_level_to_agp_type(struct drm_device *dev,

					    enum i915_cache_level cache_level)
@@ -97,7 +94,7 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj) 
	return 0;

}



static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,

void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,

				enum i915_cache_level cache_level)

{

	struct drm_device *dev = obj->base.dev;

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −2
Original line number Diff line number Diff line
@@ -236,7 +236,8 @@ init_pipe_control(struct intel_ring_buffer *ring) 
		ret = -ENOMEM;

		goto err;

	}

	obj->cache_level = I915_CACHE_LLC;



	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);



	ret = i915_gem_object_pin(obj, 4096, true);

	if (ret)
@@ -776,7 +777,8 @@ static int init_status_page(struct intel_ring_buffer *ring) 
		ret = -ENOMEM;

		goto err;

	}

	obj->cache_level = I915_CACHE_LLC;



	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);



	ret = i915_gem_object_pin(obj, 4096, true);

	if (ret != 0) {