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Commit e4f6948c authored by Kevin Corry's avatar Kevin Corry Committed by Paul Mackerras
Browse files

[POWERPC] cell: Move PMU-related stuff to include/asm-powerpc/cell-pmu.h 



Move some PMU-related macros and function prototypes from cbe_regs.h
and pmu.h in arch/powerpc/platforms/cell/ to a new header at
include/asm-powerpc/cell-pmu.h

This is cleaner to use from the oprofile code, since that sits in
arch/powerpc/oprofile, not in the cell platform directory.

Signed-off-by: default avatarKevin Corry <kevcorry@us.ibm.com>
Signed-off-by: default avatarArnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent c93dfa07

arch/powerpc/platforms/cell/cbe_regs.h

+2 −29
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#ifndef CBE_REGS_H

#define CBE_REGS_H



#include <asm/cell-pmu.h>



/*

 *

 * Some HID register definitions
@@ -35,32 +37,6 @@ 
 *

 */



/* Macros for the pm_control register. */

#define CBE_PM_16BIT_CTR(ctr)			(1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))

#define CBE_PM_ENABLE_PERF_MON			0x80000000

#define CBE_PM_STOP_AT_MAX			0x40000000

#define CBE_PM_TRACE_MODE_GET(pm_control)	(((pm_control) >> 28) & 0x3)

#define CBE_PM_TRACE_MODE_SET(mode)		(((mode)  & 0x3) << 28)

#define CBE_PM_COUNT_MODE_SET(count)		(((count) & 0x3) << 18)

#define CBE_PM_FREEZE_ALL_CTRS			0x00100000

#define CBE_PM_ENABLE_EXT_TRACE			0x00008000



/* Macros for the trace_address register. */

#define CBE_PM_TRACE_BUF_FULL			0x00000800

#define CBE_PM_TRACE_BUF_EMPTY			0x00000400

#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)		((ta) & 0x3ff)

#define CBE_PM_TRACE_BUF_MAX_COUNT		0x400



/* Macros for the pm07_control registers. */

#define CBE_PM_CTR_INPUT_MUX(pm07_control)	(((pm07_control) >> 26) & 0x3f)

#define CBE_PM_CTR_INPUT_CONTROL		0x02000000

#define CBE_PM_CTR_POLARITY			0x01000000

#define CBE_PM_CTR_COUNT_CYCLES			0x00800000

#define CBE_PM_CTR_ENABLE			0x00400000



/* Macros for the pm_status register. */

#define CBE_PM_CTR_OVERFLOW_INTR(ctr)		(1 << (31 - ((ctr) & 7)))



union spe_reg {

	u64 val;

	u8 spe[8];
@@ -160,9 +136,6 @@ extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu); 
 * counters currently have a value waiting to be written.

 */



#define NR_PHYS_CTRS	4

#define NR_CTRS		(NR_PHYS_CTRS * 2)



struct cbe_pmd_shadow_regs {

	u32 group_control;

	u32 debug_bus_control;

arch/powerpc/platforms/cell/pmu.c

+0 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 


#include "cbe_regs.h"

#include "interrupt.h"

#include "pmu.h"



/*

 * When writing to write-only mmio addresses, save a shadow copy. All of the

arch/powerpc/platforms/cell/pmu.h→include/asm-powerpc/cell-pmu.h

+90 −0
Original line number Diff line number Diff line 
/*

 * Cell Broadband Engine Performance Monitor

 *

 * (C) Copyright IBM Corporation 2001,2006

 * (C) Copyright IBM Corporation 2006

 *

 * Author:

 *   David Erb (djerb@us.ibm.com)
@@ -22,8 +22,40 @@ 
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

 */



#ifndef __PERFMON_H__

#define __PERFMON_H__

#ifndef __ASM_CELL_PMU_H__

#define __ASM_CELL_PMU_H__



/* The Cell PMU has four hardware performance counters, which can be

 * configured as four 32-bit counters or eight 16-bit counters.

 */

#define NR_PHYS_CTRS 4

#define NR_CTRS      (NR_PHYS_CTRS * 2)



/* Macros for the pm_control register. */

#define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))

#define CBE_PM_ENABLE_PERF_MON             0x80000000

#define CBE_PM_STOP_AT_MAX                 0x40000000

#define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)

#define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)

#define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)

#define CBE_PM_FREEZE_ALL_CTRS             0x00100000

#define CBE_PM_ENABLE_EXT_TRACE            0x00008000



/* Macros for the trace_address register. */

#define CBE_PM_TRACE_BUF_FULL              0x00000800

#define CBE_PM_TRACE_BUF_EMPTY             0x00000400

#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)

#define CBE_PM_TRACE_BUF_MAX_COUNT         0x400



/* Macros for the pm07_control registers. */

#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)

#define CBE_PM_CTR_INPUT_CONTROL           0x02000000

#define CBE_PM_CTR_POLARITY                0x01000000

#define CBE_PM_CTR_COUNT_CYCLES            0x00800000

#define CBE_PM_CTR_ENABLE                  0x00400000



/* Macros for the pm_status register. */

#define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))



enum pm_reg_name {

	group_control,
@@ -36,6 +68,7 @@ enum pm_reg_name { 
	pm_start_stop,

};



/* Routines for reading/writing the PMU registers. */

extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);

extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);

extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
@@ -54,4 +87,4 @@ extern void cbe_disable_pm(u32 cpu); 


extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);



#endif
 
#endif /* __ASM_CELL_PMU_H__ */