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Commit e457acae authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau: create grctx on the fly on all chipsets 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent eeb9cc01

drivers/gpu/drm/nouveau/nouveau_channel.c

+0 −10
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 
		      uint32_t vram_handle, uint32_t gart_handle)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;

	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;

	struct nouveau_channel *chan;

	unsigned long flags;
@@ -202,15 +201,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, 
	/* disable the fifo caches */

	pfifo->reassign(dev, false);



	/* Create a graphics context for new channel */

	if (dev_priv->card_type < NV_50) {

		ret = pgraph->create_context(chan);

		if (ret) {

			nouveau_channel_put(&chan);

			return ret;

		}

	}



	/* Construct inital RAMFC for new channel */

	ret = pfifo->create_context(chan);

	if (ret) {

drivers/gpu/drm/nouveau/nouveau_object.c

+2 −1
Original line number Diff line number Diff line
@@ -651,7 +651,8 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) 
		}

		break;

	case NVOBJ_ENGINE_GR:

		if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {

		if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||

		    (dev_priv->card_type  < NV_20 && !chan->pgraph_ctx)) {

			struct nouveau_pgraph_engine *pgraph =

				&dev_priv->engine.graph;

drivers/gpu/drm/nouveau/nv40_fifo.c

+0 −1
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ nv40_fifo_create_context(struct nouveau_channel *chan) 
			      NV_PFIFO_CACHE1_BIG_ENDIAN |

#endif

			      0x30000000 /* no idea.. */);

	nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);

	nv_wi32(dev, fc + 60, 0x0001FFFF);



	/* enable the fifo dma operation */

drivers/gpu/drm/nouveau/nv40_graph.c

+12 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ nv40_graph_create_context(struct nouveau_channel *chan) 
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;

	struct nouveau_grctx ctx = {};

	unsigned long flags;

	int ret;



	ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
@@ -76,6 +77,17 @@ nv40_graph_create_context(struct nouveau_channel *chan) 
	nv40_grctx_init(&ctx);



	nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);



	/* init grctx pointer in ramfc, and on PFIFO if channel is

	 * already active there

	 */

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);

	nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);

	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);

	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)

		nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);

	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);

	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	return 0;

}