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Commit e3b04bc7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drma/dmgpu: move cg and pg flags into shared headers 



So they can be used by powerplay.

Reviewed-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b118af70

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −32
Original line number Diff line number Diff line
@@ -134,38 +134,6 @@ extern unsigned amdgpu_pcie_lane_cap; 
#define AMDGPU_RESET_VCE			(1 << 13)

#define AMDGPU_RESET_VCE1			(1 << 14)



/* CG flags */

#define AMDGPU_CG_SUPPORT_GFX_MGCG		(1 << 0)

#define AMDGPU_CG_SUPPORT_GFX_MGLS		(1 << 1)

#define AMDGPU_CG_SUPPORT_GFX_CGCG		(1 << 2)

#define AMDGPU_CG_SUPPORT_GFX_CGLS		(1 << 3)

#define AMDGPU_CG_SUPPORT_GFX_CGTS		(1 << 4)

#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)

#define AMDGPU_CG_SUPPORT_GFX_CP_LS		(1 << 6)

#define AMDGPU_CG_SUPPORT_GFX_RLC_LS		(1 << 7)

#define AMDGPU_CG_SUPPORT_MC_LS			(1 << 8)

#define AMDGPU_CG_SUPPORT_MC_MGCG		(1 << 9)

#define AMDGPU_CG_SUPPORT_SDMA_LS		(1 << 10)

#define AMDGPU_CG_SUPPORT_SDMA_MGCG		(1 << 11)

#define AMDGPU_CG_SUPPORT_BIF_LS		(1 << 12)

#define AMDGPU_CG_SUPPORT_UVD_MGCG		(1 << 13)

#define AMDGPU_CG_SUPPORT_VCE_MGCG		(1 << 14)

#define AMDGPU_CG_SUPPORT_HDP_LS		(1 << 15)

#define AMDGPU_CG_SUPPORT_HDP_MGCG		(1 << 16)



/* PG flags */

#define AMDGPU_PG_SUPPORT_GFX_PG		(1 << 0)

#define AMDGPU_PG_SUPPORT_GFX_SMG		(1 << 1)

#define AMDGPU_PG_SUPPORT_GFX_DMG		(1 << 2)

#define AMDGPU_PG_SUPPORT_UVD			(1 << 3)

#define AMDGPU_PG_SUPPORT_VCE			(1 << 4)

#define AMDGPU_PG_SUPPORT_CP			(1 << 5)

#define AMDGPU_PG_SUPPORT_GDS			(1 << 6)

#define AMDGPU_PG_SUPPORT_RLC_SMU_HS		(1 << 7)

#define AMDGPU_PG_SUPPORT_SDMA			(1 << 8)

#define AMDGPU_PG_SUPPORT_ACP			(1 << 9)

#define AMDGPU_PG_SUPPORT_SAMU			(1 << 10)



/* GFX current status */

#define AMDGPU_GFX_NORMAL_MODE			0x00000000L

#define AMDGPU_GFX_SAFE_MODE			0x00000001L

drivers/gpu/drm/amd/amdgpu/cik.c

+77 −77
Original line number Diff line number Diff line
@@ -2335,72 +2335,72 @@ static int cik_common_early_init(void *handle) 
	switch (adev->asic_type) {

	case CHIP_BONAIRE:

		adev->cg_flags =

			AMDGPU_CG_SUPPORT_GFX_MGCG |

			AMDGPU_CG_SUPPORT_GFX_MGLS |

			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/

			AMDGPU_CG_SUPPORT_GFX_CGLS |

			AMDGPU_CG_SUPPORT_GFX_CGTS |

			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |

			AMDGPU_CG_SUPPORT_GFX_CP_LS |

			AMDGPU_CG_SUPPORT_MC_LS |

			AMDGPU_CG_SUPPORT_MC_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_LS |

			AMDGPU_CG_SUPPORT_BIF_LS |

			AMDGPU_CG_SUPPORT_VCE_MGCG |

			AMDGPU_CG_SUPPORT_UVD_MGCG |

			AMDGPU_CG_SUPPORT_HDP_LS |

			AMDGPU_CG_SUPPORT_HDP_MGCG;

			AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_GFX_MGLS |

			/*AMD_CG_SUPPORT_GFX_CGCG |*/

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CGTS_LS |

			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_MC_LS |

			AMD_CG_SUPPORT_MC_MGCG |

			AMD_CG_SUPPORT_SDMA_MGCG |

			AMD_CG_SUPPORT_SDMA_LS |

			AMD_CG_SUPPORT_BIF_LS |

			AMD_CG_SUPPORT_VCE_MGCG |

			AMD_CG_SUPPORT_UVD_MGCG |

			AMD_CG_SUPPORT_HDP_LS |

			AMD_CG_SUPPORT_HDP_MGCG;

		adev->pg_flags = 0;

		adev->external_rev_id = adev->rev_id + 0x14;

		break;

	case CHIP_HAWAII:

		adev->cg_flags =

			AMDGPU_CG_SUPPORT_GFX_MGCG |

			AMDGPU_CG_SUPPORT_GFX_MGLS |

			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/

			AMDGPU_CG_SUPPORT_GFX_CGLS |

			AMDGPU_CG_SUPPORT_GFX_CGTS |

			AMDGPU_CG_SUPPORT_GFX_CP_LS |

			AMDGPU_CG_SUPPORT_MC_LS |

			AMDGPU_CG_SUPPORT_MC_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_LS |

			AMDGPU_CG_SUPPORT_BIF_LS |

			AMDGPU_CG_SUPPORT_VCE_MGCG |

			AMDGPU_CG_SUPPORT_UVD_MGCG |

			AMDGPU_CG_SUPPORT_HDP_LS |

			AMDGPU_CG_SUPPORT_HDP_MGCG;

			AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_GFX_MGLS |

			/*AMD_CG_SUPPORT_GFX_CGCG |*/

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_MC_LS |

			AMD_CG_SUPPORT_MC_MGCG |

			AMD_CG_SUPPORT_SDMA_MGCG |

			AMD_CG_SUPPORT_SDMA_LS |

			AMD_CG_SUPPORT_BIF_LS |

			AMD_CG_SUPPORT_VCE_MGCG |

			AMD_CG_SUPPORT_UVD_MGCG |

			AMD_CG_SUPPORT_HDP_LS |

			AMD_CG_SUPPORT_HDP_MGCG;

		adev->pg_flags = 0;

		adev->external_rev_id = 0x28;

		break;

	case CHIP_KAVERI:

		adev->cg_flags =

			AMDGPU_CG_SUPPORT_GFX_MGCG |

			AMDGPU_CG_SUPPORT_GFX_MGLS |

			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/

			AMDGPU_CG_SUPPORT_GFX_CGLS |

			AMDGPU_CG_SUPPORT_GFX_CGTS |

			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |

			AMDGPU_CG_SUPPORT_GFX_CP_LS |

			AMDGPU_CG_SUPPORT_SDMA_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_LS |

			AMDGPU_CG_SUPPORT_BIF_LS |

			AMDGPU_CG_SUPPORT_VCE_MGCG |

			AMDGPU_CG_SUPPORT_UVD_MGCG |

			AMDGPU_CG_SUPPORT_HDP_LS |

			AMDGPU_CG_SUPPORT_HDP_MGCG;

			AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_GFX_MGLS |

			/*AMD_CG_SUPPORT_GFX_CGCG |*/

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CGTS_LS |

			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_SDMA_MGCG |

			AMD_CG_SUPPORT_SDMA_LS |

			AMD_CG_SUPPORT_BIF_LS |

			AMD_CG_SUPPORT_VCE_MGCG |

			AMD_CG_SUPPORT_UVD_MGCG |

			AMD_CG_SUPPORT_HDP_LS |

			AMD_CG_SUPPORT_HDP_MGCG;

		adev->pg_flags =

			/*AMDGPU_PG_SUPPORT_GFX_PG |

			  AMDGPU_PG_SUPPORT_GFX_SMG |

			  AMDGPU_PG_SUPPORT_GFX_DMG |*/

			AMDGPU_PG_SUPPORT_UVD |

			/*AMDGPU_PG_SUPPORT_VCE |

			  AMDGPU_PG_SUPPORT_CP |

			  AMDGPU_PG_SUPPORT_GDS |

			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |

			  AMDGPU_PG_SUPPORT_ACP |

			  AMDGPU_PG_SUPPORT_SAMU |*/

			/*AMD_PG_SUPPORT_GFX_PG |

			  AMD_PG_SUPPORT_GFX_SMG |

			  AMD_PG_SUPPORT_GFX_DMG |*/

			AMD_PG_SUPPORT_UVD |

			/*AMD_PG_SUPPORT_VCE |

			  AMD_PG_SUPPORT_CP |

			  AMD_PG_SUPPORT_GDS |

			  AMD_PG_SUPPORT_RLC_SMU_HS |

			  AMD_PG_SUPPORT_ACP |

			  AMD_PG_SUPPORT_SAMU |*/

			0;

		if (adev->pdev->device == 0x1312 ||

			adev->pdev->device == 0x1316 ||
@@ -2412,29 +2412,29 @@ static int cik_common_early_init(void *handle) 
	case CHIP_KABINI:

	case CHIP_MULLINS:

		adev->cg_flags =

			AMDGPU_CG_SUPPORT_GFX_MGCG |

			AMDGPU_CG_SUPPORT_GFX_MGLS |

			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/

			AMDGPU_CG_SUPPORT_GFX_CGLS |

			AMDGPU_CG_SUPPORT_GFX_CGTS |

			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |

			AMDGPU_CG_SUPPORT_GFX_CP_LS |

			AMDGPU_CG_SUPPORT_SDMA_MGCG |

			AMDGPU_CG_SUPPORT_SDMA_LS |

			AMDGPU_CG_SUPPORT_BIF_LS |

			AMDGPU_CG_SUPPORT_VCE_MGCG |

			AMDGPU_CG_SUPPORT_UVD_MGCG |

			AMDGPU_CG_SUPPORT_HDP_LS |

			AMDGPU_CG_SUPPORT_HDP_MGCG;

			AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_GFX_MGLS |

			/*AMD_CG_SUPPORT_GFX_CGCG |*/

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CGTS_LS |

			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_SDMA_MGCG |

			AMD_CG_SUPPORT_SDMA_LS |

			AMD_CG_SUPPORT_BIF_LS |

			AMD_CG_SUPPORT_VCE_MGCG |

			AMD_CG_SUPPORT_UVD_MGCG |

			AMD_CG_SUPPORT_HDP_LS |

			AMD_CG_SUPPORT_HDP_MGCG;

		adev->pg_flags =

			/*AMDGPU_PG_SUPPORT_GFX_PG |

			  AMDGPU_PG_SUPPORT_GFX_SMG | */

			AMDGPU_PG_SUPPORT_UVD |

			/*AMDGPU_PG_SUPPORT_VCE |

			  AMDGPU_PG_SUPPORT_CP |

			  AMDGPU_PG_SUPPORT_GDS |

			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |

			  AMDGPU_PG_SUPPORT_SAMU |*/

			/*AMD_PG_SUPPORT_GFX_PG |

			  AMD_PG_SUPPORT_GFX_SMG | */

			AMD_PG_SUPPORT_UVD |

			/*AMD_PG_SUPPORT_VCE |

			  AMD_PG_SUPPORT_CP |

			  AMD_PG_SUPPORT_GDS |

			  AMD_PG_SUPPORT_RLC_SMU_HS |

			  AMD_PG_SUPPORT_SAMU |*/

			0;

		if (adev->asic_type == CHIP_KABINI) {

			if (adev->rev_id == 0)

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+2 −2
Original line number Diff line number Diff line
@@ -885,7 +885,7 @@ static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 
{

	u32 orig, data;



	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {

		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

		WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

	} else {
@@ -906,7 +906,7 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 
{

	u32 orig, data;



	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {

		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

		data |= 0x100;

		if (orig != data)

drivers/gpu/drm/amd/amdgpu/cz_dpm.c

+3 −3
Original line number Diff line number Diff line
@@ -445,13 +445,13 @@ static int cz_dpm_init(struct amdgpu_device *adev) 
	pi->gfx_pg_threshold = 500;

	pi->caps_fps = true;

	/* uvd */

	pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;

	pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;

	pi->caps_uvd_dpm = true;

	/* vce */

	pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;

	pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;

	pi->caps_vce_dpm = true;

	/* acp */

	pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;

	pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;

	pi->caps_acp_dpm = true;



	pi->caps_stable_power_state = false;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+35 −35
Original line number Diff line number Diff line
@@ -4109,7 +4109,7 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 


	orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);



	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

		gfx_v7_0_enable_gui_idle_interrupt(adev, true);



		tmp = gfx_v7_0_halt_rlc(adev);
@@ -4147,9 +4147,9 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 
{

	u32 data, orig, tmp = 0;



	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {

		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {

			if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {

			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {

				orig = data = RREG32(mmCP_MEM_SLP_CNTL);

				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

				if (orig != data)
@@ -4176,14 +4176,14 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 


		gfx_v7_0_update_rlc(adev, tmp);



		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {

			orig = data = RREG32(mmCGTS_SM_CTRL_REG);

			data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;

			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);

			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;

			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;

			if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&

			    (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))

			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&

			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))

				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;

			data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;

			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
@@ -4249,7 +4249,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))

		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
@@ -4263,7 +4263,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))

		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
@@ -4276,7 +4276,7 @@ static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))

		data &= ~0x8000;

	else

		data |= 0x8000;
@@ -4289,7 +4289,7 @@ static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))

		data &= ~0x2000;

	else

		data |= 0x2000;
@@ -4370,7 +4370,7 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 
{

	u32 data, orig;



	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

		orig = data = RREG32(mmRLC_PG_CNTL);

		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;

		if (orig != data)
@@ -4442,7 +4442,7 @@ static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))

		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
@@ -4456,7 +4456,7 @@ static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 
	u32 data, orig;



	orig = data = RREG32(mmRLC_PG_CNTL);

	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))

		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
@@ -4623,15 +4623,15 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 


static void gfx_v7_0_init_pg(struct amdgpu_device *adev)

{

	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |

			      AMDGPU_PG_SUPPORT_GFX_SMG |

			      AMDGPU_PG_SUPPORT_GFX_DMG |

			      AMDGPU_PG_SUPPORT_CP |

			      AMDGPU_PG_SUPPORT_GDS |

			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {

	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |

			      AMD_PG_SUPPORT_GFX_SMG |

			      AMD_PG_SUPPORT_GFX_DMG |

			      AMD_PG_SUPPORT_CP |

			      AMD_PG_SUPPORT_GDS |

			      AMD_PG_SUPPORT_RLC_SMU_HS)) {

		gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);

		gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);

		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {

		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {

			gfx_v7_0_init_gfx_cgpg(adev);

			gfx_v7_0_enable_cp_pg(adev, true);

			gfx_v7_0_enable_gds_pg(adev, true);
@@ -4643,14 +4643,14 @@ static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 


static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)

{

	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |

			      AMDGPU_PG_SUPPORT_GFX_SMG |

			      AMDGPU_PG_SUPPORT_GFX_DMG |

			      AMDGPU_PG_SUPPORT_CP |

			      AMDGPU_PG_SUPPORT_GDS |

			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {

	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |

			      AMD_PG_SUPPORT_GFX_SMG |

			      AMD_PG_SUPPORT_GFX_DMG |

			      AMD_PG_SUPPORT_CP |

			      AMD_PG_SUPPORT_GDS |

			      AMD_PG_SUPPORT_RLC_SMU_HS)) {

		gfx_v7_0_update_gfx_pg(adev, false);

		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {

		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {

			gfx_v7_0_enable_cp_pg(adev, false);

			gfx_v7_0_enable_gds_pg(adev, false);

		}
@@ -5527,14 +5527,14 @@ static int gfx_v7_0_set_powergating_state(void *handle, 
	if (state == AMD_PG_STATE_GATE)

		gate = true;



	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |

			      AMDGPU_PG_SUPPORT_GFX_SMG |

			      AMDGPU_PG_SUPPORT_GFX_DMG |

			      AMDGPU_PG_SUPPORT_CP |

			      AMDGPU_PG_SUPPORT_GDS |

			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {

	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |

			      AMD_PG_SUPPORT_GFX_SMG |

			      AMD_PG_SUPPORT_GFX_DMG |

			      AMD_PG_SUPPORT_CP |

			      AMD_PG_SUPPORT_GDS |

			      AMD_PG_SUPPORT_RLC_SMU_HS)) {

		gfx_v7_0_update_gfx_pg(adev, gate);

		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {

		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {

			gfx_v7_0_enable_cp_pg(adev, gate);

			gfx_v7_0_enable_gds_pg(adev, gate);

		}