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Commit e2b80bac authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux into drm-next 

Please consider merging this tag, which contains the v4 misc fixes and add RK3399 eDP support patches[0] I sent on 2016-06-29, rebased onto v4.7-rc5.

* 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux:
  dt-bindings: analogix_dp: rockchip: correct the wrong compatible name
  drm/rockchip: analogix_dp: introduce the pclk for grf
  drm/bridge: analogix_dp: fix no drm hpd event when panel plug in
  drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode
  drm/rockchip: analogix_dp: correct the connector display color format and bpc
  drm/bridge: analogix_dp: passing the connector as an argument in .get_modes()
  drm/rockchip: analogix_dp: make panel detect to an optional action
  drm/rockchip: analogix_dp: add rk3399 eDP support
  drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
  drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
  drm/rockchip: analogix_dp: split the lcdc select setting into device data
parents d3c35337 77b8d755

Documentation/devicetree/bindings/display/bridge/analogix_dp.txt

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ Required properties for dp-controller: 
		platform specific such as:

		 * "samsung,exynos5-dp"

		 * "rockchip,rk3288-dp"

		 * "rockchip,rk3399-edp"

	-reg:

		physical base address of the controller and length

		of memory mapped region.

Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt

+8 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port 
================================



Required properties:

- compatible: "rockchip,rk3288-edp";

- compatible: "rockchip,rk3288-dp",

	      "rockchip,rk3399-edp";



- reg: physical base address of the controller and length
@@ -27,6 +28,12 @@ Required properties: 
    Port 0: contained 2 endpoints, connecting to the output of vop.

    Port 1: contained 1 endpoint, connecting to the input of panel.



Optional property for different chips:

- clocks: from common clock binding: handle to grf_vio clock.



- clock-names: from common clock binding:

	       Required elements: "grf"



For the below properties, please refer to Analogix DP binding document:

 * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

- phys (required)

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

+2 −1
Original line number Diff line number Diff line
@@ -938,7 +938,7 @@ int analogix_dp_get_modes(struct drm_connector *connector) 
		num_modes += drm_panel_get_modes(dp->plat_data->panel);



	if (dp->plat_data->get_modes)

		num_modes += dp->plat_data->get_modes(dp->plat_data);

		num_modes += dp->plat_data->get_modes(dp->plat_data, connector);



	return num_modes;

}
@@ -1208,6 +1208,7 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) 


	switch (dp->plat_data->dev_type) {

	case RK3288_DP:

	case RK3399_EDP:

		/*

		 * Like Rk3288 DisplayPort TRM indicate that "Main link

		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".

drivers/gpu/drm/bridge/analogix/analogix_dp_core.h

+4 −4
Original line number Diff line number Diff line
@@ -127,10 +127,10 @@ enum analog_power_block { 
};



enum dp_irq_type {

	DP_IRQ_TYPE_HP_CABLE_IN,

	DP_IRQ_TYPE_HP_CABLE_OUT,

	DP_IRQ_TYPE_HP_CHANGE,

	DP_IRQ_TYPE_UNKNOWN,

	DP_IRQ_TYPE_HP_CABLE_IN  = BIT(0),

	DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),

	DP_IRQ_TYPE_HP_CHANGE    = BIT(2),

	DP_IRQ_TYPE_UNKNOWN      = BIT(3),

};



struct video_info {

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

+8 −4
Original line number Diff line number Diff line
@@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 
	reg = SEL_24M | TX_DVDD_BIT_1_0625V;

	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);



	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {

		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);

	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {

		reg = REF_CLK_24M;

		if (dp->plat_data->dev_type == RK3288_DP)

			reg ^= REF_CLK_MASK;



		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);

		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);

		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);

		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
@@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 
	u32 reg;

	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;



	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))

	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

		phy_pd_addr = ANALOGIX_DP_PD;



	switch (block) {
@@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) 
	analogix_dp_reset_aux(dp);



	/* Disable AUX transaction H/W retry */

	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))

	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |

		      AUX_HW_RETRY_COUNT_SEL(3) |

		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;