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Commit e285bca6 authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Tony Lindgren
Browse files

omap: mcbsp: Drop SPI mode support 



We haven't seen any use for the SPI API in McBSP driver over the years. More
over, Peter Ujfalusi <peter.ujfalusi@ti.com> noticed that SPI mode is not
even supported since OMAP2430 so it's very unlikely that we'll see any use
for it in the future either.

Signed-off-by: default avatarJarkko Nikula <jhnikula@gmail.com>
Acked-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent d19f579a

arch/arm/plat-omap/include/plat/mcbsp.h

+0 −37
Original line number Diff line number Diff line
@@ -353,38 +353,6 @@ typedef enum { 
	OMAP_MCBSP_WORD_32,

} omap_mcbsp_word_length;



typedef enum {

	OMAP_MCBSP_CLK_RISING = 0,

	OMAP_MCBSP_CLK_FALLING,

} omap_mcbsp_clk_polarity;



typedef enum {

	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,

	OMAP_MCBSP_FS_ACTIVE_LOW,

} omap_mcbsp_fs_polarity;



typedef enum {

	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,

	OMAP_MCBSP_CLK_STP_MODE_DELAY,

} omap_mcbsp_clk_stp_mode;





/******* SPI specific mode **********/

typedef enum {

	OMAP_MCBSP_SPI_MASTER = 0,

	OMAP_MCBSP_SPI_SLAVE,

} omap_mcbsp_spi_mode;



struct omap_mcbsp_spi_cfg {

	omap_mcbsp_spi_mode		spi_mode;

	omap_mcbsp_clk_polarity		rx_clock_polarity;

	omap_mcbsp_clk_polarity		tx_clock_polarity;

	omap_mcbsp_fs_polarity		fsx_polarity;

	u8				clk_div;

	omap_mcbsp_clk_stp_mode		clk_stp_mode;

	omap_mcbsp_word_length		word_length;

};



/* Platform specific configuration */

struct omap_mcbsp_ops {

	void (*request)(unsigned int);
@@ -504,14 +472,9 @@ u32 omap_mcbsp_recv_word(unsigned int id); 


int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);

int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);

int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);

int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);





/* McBSP functional clock source changing function */

extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);

/* SPI specific API */

void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);



/* Polled read/write functions */

int omap_mcbsp_pollread(unsigned int id, u16 * buf);

arch/arm/plat-omap/mcbsp.c

+0 −214
Original line number Diff line number Diff line
@@ -1175,147 +1175,6 @@ u32 omap_mcbsp_recv_word(unsigned int id) 
}

EXPORT_SYMBOL(omap_mcbsp_recv_word);



int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)

{

	struct omap_mcbsp *mcbsp;

	omap_mcbsp_word_length tx_word_length;

	omap_mcbsp_word_length rx_word_length;

	u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;



	if (!omap_mcbsp_check_valid_id(id)) {

		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

		return -ENODEV;

	}

	mcbsp = id_to_mcbsp_ptr(id);

	tx_word_length = mcbsp->tx_word_length;

	rx_word_length = mcbsp->rx_word_length;



	if (tx_word_length != rx_word_length)

		return -EINVAL;



	/* First we wait for the transmitter to be ready */

	spcr2 = MCBSP_READ(mcbsp, SPCR2);

	while (!(spcr2 & XRDY)) {

		spcr2 = MCBSP_READ(mcbsp, SPCR2);

		if (attempts++ > 1000) {

			/* We must reset the transmitter */

			MCBSP_WRITE(mcbsp, SPCR2,

				    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));

			udelay(10);

			MCBSP_WRITE(mcbsp, SPCR2,

				    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);

			udelay(10);

			dev_err(mcbsp->dev, "McBSP%d transmitter not "

				"ready\n", mcbsp->id);

			return -EAGAIN;

		}

	}



	/* Now we can push the data */

	if (tx_word_length > OMAP_MCBSP_WORD_16)

		MCBSP_WRITE(mcbsp, DXR2, word >> 16);

	MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);



	/* We wait for the receiver to be ready */

	spcr1 = MCBSP_READ(mcbsp, SPCR1);

	while (!(spcr1 & RRDY)) {

		spcr1 = MCBSP_READ(mcbsp, SPCR1);

		if (attempts++ > 1000) {

			/* We must reset the receiver */

			MCBSP_WRITE(mcbsp, SPCR1,

				    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));

			udelay(10);

			MCBSP_WRITE(mcbsp, SPCR1,

				    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);

			udelay(10);

			dev_err(mcbsp->dev, "McBSP%d receiver not "

				"ready\n", mcbsp->id);

			return -EAGAIN;

		}

	}



	/* Receiver is ready, let's read the dummy data */

	if (rx_word_length > OMAP_MCBSP_WORD_16)

		word_msb = MCBSP_READ(mcbsp, DRR2);

	word_lsb = MCBSP_READ(mcbsp, DRR1);



	return 0;

}

EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);



int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)

{

	struct omap_mcbsp *mcbsp;

	u32 clock_word = 0;

	omap_mcbsp_word_length tx_word_length;

	omap_mcbsp_word_length rx_word_length;

	u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;



	if (!omap_mcbsp_check_valid_id(id)) {

		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

		return -ENODEV;

	}



	mcbsp = id_to_mcbsp_ptr(id);



	tx_word_length = mcbsp->tx_word_length;

	rx_word_length = mcbsp->rx_word_length;



	if (tx_word_length != rx_word_length)

		return -EINVAL;



	/* First we wait for the transmitter to be ready */

	spcr2 = MCBSP_READ(mcbsp, SPCR2);

	while (!(spcr2 & XRDY)) {

		spcr2 = MCBSP_READ(mcbsp, SPCR2);

		if (attempts++ > 1000) {

			/* We must reset the transmitter */

			MCBSP_WRITE(mcbsp, SPCR2,

				    MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));

			udelay(10);

			MCBSP_WRITE(mcbsp, SPCR2,

				    MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);

			udelay(10);

			dev_err(mcbsp->dev, "McBSP%d transmitter not "

				"ready\n", mcbsp->id);

			return -EAGAIN;

		}

	}



	/* We first need to enable the bus clock */

	if (tx_word_length > OMAP_MCBSP_WORD_16)

		MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);

	MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);



	/* We wait for the receiver to be ready */

	spcr1 = MCBSP_READ(mcbsp, SPCR1);

	while (!(spcr1 & RRDY)) {

		spcr1 = MCBSP_READ(mcbsp, SPCR1);

		if (attempts++ > 1000) {

			/* We must reset the receiver */

			MCBSP_WRITE(mcbsp, SPCR1,

				    MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));

			udelay(10);

			MCBSP_WRITE(mcbsp, SPCR1,

				    MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);

			udelay(10);

			dev_err(mcbsp->dev, "McBSP%d receiver not "

				"ready\n", mcbsp->id);

			return -EAGAIN;

		}

	}



	/* Receiver is ready, there is something for us */

	if (rx_word_length > OMAP_MCBSP_WORD_16)

		word_msb = MCBSP_READ(mcbsp, DRR2);

	word_lsb = MCBSP_READ(mcbsp, DRR1);



	word[0] = (word_lsb | (word_msb << 16));



	return 0;

}

EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);



/*

 * Simple DMA based buffer rx/tx routines.

 * Nothing fancy, just a single buffer tx/rx through DMA.
@@ -1449,79 +1308,6 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, 
}

EXPORT_SYMBOL(omap_mcbsp_recv_buffer);



/*

 * SPI wrapper.

 * Since SPI setup is much simpler than the generic McBSP one,

 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.

 * Once this is done, you can call omap_mcbsp_start().

 */

void omap_mcbsp_set_spi_mode(unsigned int id,

				const struct omap_mcbsp_spi_cfg *spi_cfg)

{

	struct omap_mcbsp *mcbsp;

	struct omap_mcbsp_reg_cfg mcbsp_cfg;



	if (!omap_mcbsp_check_valid_id(id)) {

		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

		return;

	}

	mcbsp = id_to_mcbsp_ptr(id);



	memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));



	/* SPI has only one frame */

	mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));

	mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));



	/* Clock stop mode */

	if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)

		mcbsp_cfg.spcr1 |= (1 << 12);

	else

		mcbsp_cfg.spcr1 |= (3 << 11);



	/* Set clock parities */

	if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)

		mcbsp_cfg.pcr0 |= CLKRP;

	else

		mcbsp_cfg.pcr0 &= ~CLKRP;



	if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)

		mcbsp_cfg.pcr0 &= ~CLKXP;

	else

		mcbsp_cfg.pcr0 |= CLKXP;



	/* Set SCLKME to 0 and CLKSM to 1 */

	mcbsp_cfg.pcr0 &= ~SCLKME;

	mcbsp_cfg.srgr2 |= CLKSM;



	/* Set FSXP */

	if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)

		mcbsp_cfg.pcr0 &= ~FSXP;

	else

		mcbsp_cfg.pcr0 |= FSXP;



	if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {

		mcbsp_cfg.pcr0 |= CLKXM;

		mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);

		mcbsp_cfg.pcr0 |= FSXM;

		mcbsp_cfg.srgr2 &= ~FSGM;

		mcbsp_cfg.xcr2 |= XDATDLY(1);

		mcbsp_cfg.rcr2 |= RDATDLY(1);

	} else {

		mcbsp_cfg.pcr0 &= ~CLKXM;

		mcbsp_cfg.srgr1 |= CLKGDV(1);

		mcbsp_cfg.pcr0 &= ~FSXM;

		mcbsp_cfg.xcr2 &= ~XDATDLY(3);

		mcbsp_cfg.rcr2 &= ~RDATDLY(3);

	}



	mcbsp_cfg.xcr2 &= ~XPHASE;

	mcbsp_cfg.rcr2 &= ~RPHASE;



	omap_mcbsp_config(id, &mcbsp_cfg);

}

EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);



#ifdef CONFIG_ARCH_OMAP3

#define max_thres(m)			(mcbsp->pdata->buffer_size)

#define valid_threshold(m, val)		((val) <= max_thres(m))