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Commit e25bda56 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce/AMD: Fix UP build error
  x86: Specify a size for the cmp in the NMI handler
  x86/nmi: Test saved %cs in NMI to determine nested NMI case
  x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors
  x86/microcode: Remove noisy AMD microcode warning
parents 70ca00db 3f806e50
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+36 −8
Original line number Diff line number Diff line
@@ -326,8 +326,7 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb)
	l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
}

static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf,
					int index)
static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
{
	int node;

@@ -725,14 +724,16 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
#define CPUID4_INFO_IDX(x, y)	(&((per_cpu(ici_cpuid4_info, x))[y]))

#ifdef CONFIG_SMP
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)

static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
{
	struct _cpuid4_info	*this_leaf, *sibling_leaf;
	unsigned long num_threads_sharing;
	int index_msb, i, sibling;
	struct _cpuid4_info *this_leaf;
	int ret, i, sibling;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
	ret = 0;
	if (index == 3) {
		ret = 1;
		for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
			if (!per_cpu(ici_cpuid4_info, i))
				continue;
@@ -743,8 +744,35 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
				set_bit(sibling, this_leaf->shared_cpu_map);
			}
		}
	} else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
		ret = 1;
		for_each_cpu(i, cpu_sibling_mask(cpu)) {
			if (!per_cpu(ici_cpuid4_info, i))
				continue;
			this_leaf = CPUID4_INFO_IDX(i, index);
			for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
				if (!cpu_online(sibling))
					continue;
				set_bit(sibling, this_leaf->shared_cpu_map);
			}
		}
	}

	return ret;
}

static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
{
	struct _cpuid4_info *this_leaf, *sibling_leaf;
	unsigned long num_threads_sharing;
	int index_msb, i;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	if (c->x86_vendor == X86_VENDOR_AMD) {
		if (cache_shared_amd_cpu_map_setup(cpu, index))
			return;
	}

	this_leaf = CPUID4_INFO_IDX(cpu, index);
	num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing;

+2 −0
Original line number Diff line number Diff line
@@ -528,6 +528,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)

	sprintf(name, "threshold_bank%i", bank);

#ifdef CONFIG_SMP
	if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {	/* symlink */
		i = cpumask_first(cpu_llc_shared_mask(cpu));

@@ -553,6 +554,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)

		goto out;
	}
#endif

	b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
	if (!b) {
+8 −1
Original line number Diff line number Diff line
@@ -1531,11 +1531,18 @@ ENTRY(nmi)
	/* Use %rdx as out temp variable throughout */
	pushq_cfi %rdx

	/*
	 * If %cs was not the kernel segment, then the NMI triggered in user
	 * space, which means it is definitely not nested.
	 */
	cmpl $__KERNEL_CS, 16(%rsp)
	jne first_nmi

	/*
	 * Check the special variable on the stack to see if NMIs are
	 * executing.
	 */
	cmp $1, -8(%rsp)
	cmpl $1, -8(%rsp)
	je nested_nmi

	/*
+0 −1
Original line number Diff line number Diff line
@@ -360,7 +360,6 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device)
static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
	return UCODE_ERROR;
}