Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e1a08b85 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull ARM64 fixes from Catalin Marinas:
 - Exception level check at boot time (for completeness, not triggering
   any bug before)
 - I/D-cache synchronisation logic for huge pages
 - Config symbol typo

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: fix el2_setup check of CurrentEL
  arm64: mm: Make icache synchronisation logic huge page aware
  arm64: mm: Fix horrendous config typo
parents 77c4cf17 974c8e45

arch/arm64/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 
#define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \

				 PMD_TYPE_SECT)



#ifdef ARM64_64K_PAGES

#ifdef CONFIG_ARM64_64K_PAGES

#define pud_sect(pud)		(0)

#else

#define pud_sect(pud)		((pud_val(pud) & PUD_TYPE_MASK) == \

arch/arm64/include/asm/ptrace.h

+4 −0
Original line number Diff line number Diff line
@@ -21,6 +21,10 @@ 


#include <uapi/asm/ptrace.h>



/* Current Exception Level values, as contained in CurrentEL */

#define CurrentEL_EL1		(1 << 2)

#define CurrentEL_EL2		(2 << 2)



/* AArch32-specific ptrace requests */

#define COMPAT_PTRACE_GETREGS		12

#define COMPAT_PTRACE_SETREGS		13

arch/arm64/kernel/efi-entry.S

+1 −2
Original line number Diff line number Diff line
@@ -78,8 +78,7 @@ ENTRY(efi_stub_entry) 


	/* Turn off Dcache and MMU */

	mrs	x0, CurrentEL

	cmp	x0, #PSR_MODE_EL2t

	ccmp	x0, #PSR_MODE_EL2h, #0x4, ne

	cmp	x0, #CurrentEL_EL2

	b.ne	1f

	mrs	x0, sctlr_el2

	bic	x0, x0, #1 << 0	// clear SCTLR.M

arch/arm64/kernel/head.S

+1 −2
Original line number Diff line number Diff line
@@ -270,8 +270,7 @@ ENDPROC(stext) 
 */

ENTRY(el2_setup)

	mrs	x0, CurrentEL

	cmp	x0, #PSR_MODE_EL2t

	ccmp	x0, #PSR_MODE_EL2h, #0x4, ne

	cmp	x0, #CurrentEL_EL2

	b.ne	1f

	mrs	x0, sctlr_el2

CPU_BE(	orr	x0, x0, #(1 << 25)	)	// Set the EE bit for EL2

arch/arm64/mm/flush.c

+2 −1
Original line number Diff line number Diff line
@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr) 
		return;



	if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {

		__flush_dcache_area(page_address(page), PAGE_SIZE);

		__flush_dcache_area(page_address(page),

				PAGE_SIZE << compound_order(page));

		__flush_icache_all();

	} else if (icache_is_aivivt()) {

		__flush_icache_all();