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Commit e0ee1a75 authored by Victor(Weiguo) Pan's avatar Victor(Weiguo) Pan Committed by Thierry Reding
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pwm: tegra: Allow 100 % duty cycle 



To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: default avatarVictor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 5dfbd2bd

drivers/pwm/pwm-tegra.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the

	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the

	 * nearest integer during division.

	 * nearest integer during division.

	 */

	 */

	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;

	c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;

	do_div(c, period_ns);

	do_div(c, period_ns);





	val = (u32)c << PWM_DUTY_SHIFT;

	val = (u32)c << PWM_DUTY_SHIFT;