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Commit e05c5a31 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau: tidy ram{ht,fc,ro} a bit 



Reviewed-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent fbd2895e

drivers/gpu/drm/nouveau/nouveau_drv.h

+4 −8
Original line number Diff line number Diff line
@@ -546,14 +546,10 @@ struct drm_nouveau_private { 


	/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */

	struct nouveau_ramht  *ramht;

	struct nouveau_gpuobj *ramfc;

	struct nouveau_gpuobj *ramro;



	uint32_t ramin_rsvd_vram;

	uint32_t ramht_offset;

	uint32_t ramht_size;

	uint32_t ramht_bits;

	uint32_t ramfc_offset;

	uint32_t ramfc_size;

	uint32_t ramro_offset;

	uint32_t ramro_size;



	struct {

		enum {

drivers/gpu/drm/nouveau/nouveau_object.c

+0 −2
Original line number Diff line number Diff line
@@ -192,8 +192,6 @@ nouveau_gpuobj_takedown(struct drm_device *dev) 
	struct drm_nouveau_private *dev_priv = dev->dev_private;



	NV_DEBUG(dev, "\n");



	nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);

}



void

drivers/gpu/drm/nouveau/nouveau_ramht.c

+13 −10
Original line number Diff line number Diff line
@@ -28,21 +28,23 @@ 
#include "nouveau_ramht.h"



static uint32_t

nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)

nouveau_ramht_hash_handle(struct nouveau_channel *chan, uint32_t handle)

{

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_ramht *ramht = chan->ramht;

	uint32_t hash = 0;

	int i;



	NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);

	NV_DEBUG(dev, "ch%d handle=0x%08x\n", chan->id, handle);



	for (i = 32; i > 0; i -= dev_priv->ramht_bits) {

		hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));

		handle >>= dev_priv->ramht_bits;

	for (i = 32; i > 0; i -= ramht->bits) {

		hash ^= (handle & ((1 << ramht->bits) - 1));

		handle >>= ramht->bits;

	}



	if (dev_priv->card_type < NV_50)

		hash ^= channel << (dev_priv->ramht_bits - 4);

		hash ^= chan->id << (ramht->bits - 4);

	hash <<= 3;



	NV_DEBUG(dev, "hash=0x%08x\n", hash);
@@ -103,7 +105,7 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle, 
		}

	}



	co = ho = nouveau_ramht_hash_handle(dev, chan->id, handle);

	co = ho = nouveau_ramht_hash_handle(chan, handle);

	do {

		if (!nouveau_ramht_entry_valid(dev, ramht, co)) {

			NV_DEBUG(dev,
@@ -119,7 +121,7 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle, 
			 chan->id, co, nv_ro32(ramht, co));



		co += 8;

		if (co >= dev_priv->ramht_size)

		if (co >= ramht->size)

			co = 0;

	} while (co != ho);
@@ -149,7 +151,7 @@ nouveau_ramht_remove(struct nouveau_channel *chan, u32 handle) 
		break;

	}



	co = ho = nouveau_ramht_hash_handle(dev, chan->id, handle);

	co = ho = nouveau_ramht_hash_handle(chan, handle);

	do {

		if (nouveau_ramht_entry_valid(dev, ramht, co) &&

		    (handle == nv_ro32(ramht, co))) {
@@ -163,7 +165,7 @@ nouveau_ramht_remove(struct nouveau_channel *chan, u32 handle) 
		}



		co += 8;

		if (co >= dev_priv->ramht_size)

		if (co >= ramht->size)

			co = 0;

	} while (co != ho);
@@ -196,6 +198,7 @@ nouveau_ramht_new(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, 


	ramht->dev = dev;

	ramht->refcount = 1;

	ramht->bits = drm_order(gpuobj->size / 8);

	INIT_LIST_HEAD(&ramht->entries);

	nouveau_gpuobj_ref(gpuobj, &ramht->gpuobj);

drivers/gpu/drm/nouveau/nouveau_ramht.h

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct nouveau_ramht { 
	int refcount;

	struct nouveau_gpuobj *gpuobj;

	struct list_head entries;

	int bits;

};



extern int  nouveau_ramht_new(struct drm_device *, struct nouveau_gpuobj *,

drivers/gpu/drm/nouveau/nv04_fifo.c

+6 −5
Original line number Diff line number Diff line
@@ -27,8 +27,9 @@ 
#include "drmP.h"

#include "drm.h"

#include "nouveau_drv.h"

#include "nouveau_ramht.h"



#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))

#define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))

#define NV04_RAMFC__SIZE 32

#define NV04_RAMFC_DMA_PUT                                       0x00

#define NV04_RAMFC_DMA_GET                                       0x04
@@ -262,10 +263,10 @@ nv04_fifo_init_ramxx(struct drm_device *dev) 
	struct drm_nouveau_private *dev_priv = dev->dev_private;



	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |

				       ((dev_priv->ramht_bits - 9) << 16) |

				       (dev_priv->ramht_offset >> 8));

	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);

	nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);

				       ((dev_priv->ramht->bits - 9) << 16) |

				       (dev_priv->ramht->gpuobj->pinst >> 8));

	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);

	nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);

}



static void