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Commit dfd7aecf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2014-07-03' of git://anongit.freedesktop.org/drm-intel 

Fixes for 3.16-rc3; most importantly Jesse brings back VGA he took away
on a bunch of machines. Also a vblank fix for BDW and a power workaround
fix for VLV.

* tag 'drm-intel-fixes-2014-07-03' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Drop early VLV WA to fix Voltage not getting dropped to Vmin
  drm/i915: only apply crt_present check on VLV
  drm/i915: Wait for vblank after enabling the primary plane on BDW
parents 80e6e6b1 5549d25f

drivers/gpu/drm/i915/intel_display.c

+26 −1
Original line number Diff line number Diff line
@@ -2087,6 +2087,7 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 
static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,

					  enum plane plane, enum pipe pipe)

{

	struct drm_device *dev = dev_priv->dev;

	struct intel_crtc *intel_crtc =

		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

	int reg;
@@ -2106,6 +2107,14 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, 


	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

	intel_flush_primary_plane(dev_priv, plane);



	/*

	 * BDW signals flip done immediately if the plane

	 * is disabled, even if the plane enable is already

	 * armed to occur at the next vblank :(

	 */

	if (IS_BROADWELL(dev))

		intel_wait_for_vblank(dev, intel_crtc->pipe);

}



/**
@@ -11088,6 +11097,22 @@ const char *intel_output_name(int output) 
	return names[output];

}



static bool intel_crt_present(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_ULT(dev))

		return false;



	if (IS_CHERRYVIEW(dev))

		return false;



	if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)

		return false;



	return true;

}



static void intel_setup_outputs(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -11096,7 +11121,7 @@ static void intel_setup_outputs(struct drm_device *dev) 


	intel_lvds_init(dev);



	if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)

	if (intel_crt_present(dev))

		intel_crt_init(dev);



	if (HAS_DDI(dev)) {

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -3209,6 +3209,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
*/

static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;



	/* Latest VLV doesn't need to force the gfx clock */

	if (dev->pdev->revision >= 0xd) {

		valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);

		return;

	}



	/*

	 * When we are idle.  Drop to min voltage state.

	 */

drivers/gpu/drm/i915/intel_sprite.c

+8 −0
Original line number Diff line number Diff line
@@ -690,6 +690,14 @@ intel_post_enable_primary(struct drm_crtc *crtc) 
	struct drm_device *dev = crtc->dev;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);



	/*

	 * BDW signals flip done immediately if the plane

	 * is disabled, even if the plane enable is already

	 * armed to occur at the next vblank :(

	 */

	if (IS_BROADWELL(dev))

		intel_wait_for_vblank(dev, intel_crtc->pipe);



	/*

	 * FIXME IPS should be fine as long as one plane is

	 * enabled, but in practice it seems to have problems