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Commit df56556e authored by Rajendra Nayak's avatar Rajendra Nayak Committed by paul
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OMAP3 SDRC: Move the clk stabilization delay to the right place 



The clock stabilization delay post a M2 divider change is needed
even before a SDRC interface clock re-enable and not only before
jumping back to SDRAM.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 8ff120e5

arch/arm/mach-omap2/sram34xx.S

+2 −2
Original line number Diff line number Diff line
@@ -127,6 +127,8 @@ skip_cs1_params: 
	blne	lock_dll

	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC

	bl 	configure_core_dpll	@ change the DPLL3 M2 divider

	mov	r12, r2

	bl	wait_clk_stable		@ wait for SDRC to stabilize

	bl	enable_sdrc		@ take SDRC out of idle

	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change

	bleq	wait_dll_unlock
@@ -134,8 +136,6 @@ skip_cs1_params: 
	cmp	r3, #1			@ if increasing SDRC clk rate,

	beq	return_to_sdram		@ return to SDRAM code, otherwise,

	bl	configure_sdrc		@ reprogram SDRC regs now

	mov	r12, r2

	bl	wait_clk_stable		@ wait for SDRC to stabilize

return_to_sdram:

	isb				@ prevent speculative exec past here

	mov 	r0, #0 			@ return value