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Commit deb9b4ce authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm: (31 commits)
  ARM: 7304/1: ioremap: fix boundary check when reusing static mapping
  ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts
  ARM: 7299/1: ftrace: clear zero bit in reported IPs for Thumb-2
  ARM: 7298/1: realview: fix mapping of MPCore private memory region
  PCMCIA: fix sa1111 oops on remove
  ARM: 7288/1: mach-sa1100: add missing module_init() call
  ARM: 7297/1: smp_twd: make sure timer is stopped before registering it
  ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
  ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE block
  ARM: 7293/1: logical_cpu_map: decouple CPU mapping from SMP
  ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs
  ARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary
  ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
  MFD: ucb1x00-ts: fix resume failure
  MFD: ucb1x00-core: fix gpiolib direction_output handling
  MFD: ucb1x00-core: fix missing restore of io output data on resume
  MFD: mcp-core: fix mcp_priv() to be more type safe
  MFD: mcp-core: fix complaints from the genirq layer
  Revert "ARM: sa11x0: Implement autoloading of codec and codec pdata for mcp bus."
  Revert "ARM: sa1100: Refactor mcp-sa11x0 to use platform resources."
  ...

Fix up conflict due to arch/arm/mach-mx5/Kconfig having been merged into
mach-imx5 (commit 784a90c0: "ARM i.MX: Merge i.MX5 support into
mach-imx"), but the ARM_L1_CACHE_SHIFT_6 entry was moved to be driven by
the CPU_V7 logic from it in the old location in rmk's branch (commit
a092f2b1: "ARM: 7291/1: cache: assume 64-byte L1 cachelines for
ARMv7 CPUs").
parents 81bc3009 3c424f35

arch/arm/Kconfig

+1 −3
Original line number Diff line number Diff line
@@ -754,7 +754,7 @@ config ARCH_SA1100 
	select ARCH_HAS_CPUFREQ

	select CPU_FREQ

	select GENERIC_CLOCKEVENTS

	select CLKDEV_LOOKUP

	select HAVE_CLK

	select HAVE_SCHED_CLOCK

	select TICK_ONESHOT

	select ARCH_REQUIRE_GPIOLIB
@@ -825,7 +825,6 @@ config ARCH_S5PC100 
	select HAVE_CLK

	select CLKDEV_LOOKUP

	select CPU_V7

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_USES_GETTIMEOFFSET

	select HAVE_S3C2410_I2C if I2C

	select HAVE_S3C_RTC if RTC_CLASS
@@ -842,7 +841,6 @@ config ARCH_S5PV210 
	select HAVE_CLK

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS

	select HAVE_SCHED_CLOCK

arch/arm/common/gic.c

+2 −5
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 


#include <asm/irq.h>

#include <asm/exception.h>

#include <asm/smp_plat.h>

#include <asm/mach/irq.h>

#include <asm/hardware/gic.h>
@@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) 
	unsigned int gic_irqs = gic->gic_irqs;

	struct irq_domain *domain = &gic->domain;

	void __iomem *base = gic_data_dist_base(gic);

	u32 cpu = 0;



#ifdef CONFIG_SMP

	cpu = cpu_logical_map(smp_processor_id());

#endif

	u32 cpu = cpu_logical_map(smp_processor_id());



	cpumask = 1 << cpu;

	cpumask |= cpumask << 8;

arch/arm/include/asm/assembler.h

+2 −2
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ 
 */

#ifdef CONFIG_THUMB2_KERNEL



	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()

	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()

9999:

	.if	\inc == 1

	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
@@ -277,7 +277,7 @@ 


#else	/* !CONFIG_THUMB2_KERNEL */



	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()

	.rept	\rept

9999:

	.if	\inc == 1

arch/arm/include/asm/domain.h

+4 −4
Original line number Diff line number Diff line
@@ -83,9 +83,9 @@ 
 * instructions (inline assembly)

 */

#ifdef CONFIG_CPU_USE_DOMAINS

#define T(instr)	#instr "t"

#define TUSER(instr)	#instr "t"

#else

#define T(instr)	#instr

#define TUSER(instr)	#instr

#endif



#else /* __ASSEMBLY__ */
@@ -95,9 +95,9 @@ 
 * instructions

 */

#ifdef CONFIG_CPU_USE_DOMAINS

#define T(instr)	instr ## t

#define TUSER(instr)	instr ## t

#else

#define T(instr)	instr

#define TUSER(instr)	instr

#endif



#endif /* __ASSEMBLY__ */

arch/arm/include/asm/futex.h

+4 −4
Original line number Diff line number Diff line
@@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 


#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)	\

	__asm__ __volatile__(					\

	"1:	" T(ldr) "	%1, [%3]\n"			\

	"1:	" TUSER(ldr) "	%1, [%3]\n"			\

	"	" insn "\n"					\

	"2:	" T(str) "	%0, [%3]\n"			\

	"2:	" TUSER(str) "	%0, [%3]\n"			\

	"	mov	%0, #0\n"				\

	__futex_atomic_ex_table("%5")				\

	: "=&r" (ret), "=&r" (oldval), "=&r" (tmp)		\
@@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 
		return -EFAULT;



	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"

	"1:	" T(ldr) "	%1, [%4]\n"

	"1:	" TUSER(ldr) "	%1, [%4]\n"

	"	teq	%1, %2\n"

	"	it	eq	@ explicit IT needed for the 2b label\n"

	"2:	" T(streq) "	%3, [%4]\n"

	"2:	" TUSER(streq) "	%3, [%4]\n"

	__futex_atomic_ex_table("%5")

	: "+r" (ret), "=&r" (val)

	: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)