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Commit de8e71ca authored by Russell King's avatar Russell King
Browse files

ARM: pm: only use preallocated page table during resume 



Only use the preallocated page table during the resume, not while
suspending.  This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.

Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarShawn Guo <shawn.guo@linaro.org>
Tested-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e8ce0eb5

arch/arm/kernel/sleep.S

+9 −10
Original line number Diff line number Diff line
@@ -9,12 +9,14 @@ 


/*

 * Save CPU state for a suspend

 *  r0 = phys addr of temporary page tables

 *  r1 = v:p offset

 *  r2 = suspend function arg0

 *  r3 = suspend function

 */

ENTRY(__cpu_suspend)

	stmfd	sp!, {r4 - r11, lr}

	mov	r4, r0

#ifdef MULTI_CPU

	ldr	r10, =processor

	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
@@ -27,7 +29,7 @@ ENTRY(__cpu_suspend) 
	sub	sp, sp, r5		@ allocate CPU state on stack

	mov	r0, sp			@ save pointer to CPU save block

	add	ip, ip, r1		@ convert resume fn to phys

	stmfd	sp!, {r6, ip}		@ save virt SP, phys resume fn

	stmfd	sp!, {r4, r6, ip}	@ save phys pgd, virt SP, phys resume fn

	ldr	r5, =sleep_save_sp

	add	r6, sp, r1		@ convert SP to phys

	stmfd	sp!, {r2, r3}		@ save suspend func arg and pointer
@@ -60,7 +62,7 @@ ENDPROC(__cpu_suspend) 
	.ltorg



cpu_suspend_abort:

	ldmia	sp!, {r2 - r3}		@ pop virt SP, phys resume fn

	ldmia	sp!, {r1 - r3}		@ pop phys pgd, virt SP, phys resume fn

	teq	r0, #0

	moveq	r0, #1			@ force non-zero value

	mov	sp, r2
@@ -69,9 +71,6 @@ ENDPROC(cpu_suspend_abort) 


/*

 * r0 = control register value

 * r1 = v:p offset (preserved by cpu_do_resume)

 * r2 = phys page table base

 * r3 = L1 section flags

 */

ENTRY(cpu_resume_mmu)

	ldr	r3, =cpu_resume_after_mmu
@@ -112,9 +111,9 @@ ENTRY(cpu_resume) 
	ldr	r0, sleep_save_sp	@ stack phys addr

#endif

	setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off

	@ load stack, resume fn

  ARM(	ldmia	r0!, {sp, pc}	)

THUMB(	ldmia	r0!, {r2, r3}	)

	@ load phys pgd, stack, resume fn

  ARM(	ldmia	r0!, {r1, sp, pc}	)

THUMB(	ldmia	r0!, {r1, r2, r3}	)

THUMB(	mov	sp, r2			)

THUMB(	bx	r3			)

ENDPROC(cpu_resume)

arch/arm/kernel/suspend.c

+10 −7
Original line number Diff line number Diff line
@@ -24,14 +24,17 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) 
		return -EINVAL;



	/*

	 * Temporarily switch the page tables to our suspend page

	 * tables, which contain the temporary identity mapping

	 * required for resuming.

	 * Provide a temporary page table with an identity mapping for

	 * the MMU-enable code, required for resuming.  On successful

	 * resume (indicated by a zero return code), we need to switch

	 * back to the correct page tables.

	 */

	cpu_switch_mm(suspend_pgd, mm);

	ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);

	ret = __cpu_suspend(virt_to_phys(suspend_pgd),

			    PHYS_OFFSET - PAGE_OFFSET, arg, fn);

	if (ret == 0) {

		cpu_switch_mm(mm->pgd, mm);

		local_flush_tlb_all();

	}



	return ret;

}

arch/arm/mm/proc-arm920.S

+8 −9
Original line number Diff line number Diff line
@@ -379,27 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext) 


/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */

.globl	cpu_arm920_suspend_size

.equ	cpu_arm920_suspend_size, 4 * 4

.equ	cpu_arm920_suspend_size, 4 * 3

#ifdef CONFIG_PM_SLEEP

ENTRY(cpu_arm920_do_suspend)

	stmfd	sp!, {r4 - r7, lr}

	stmfd	sp!, {r4 - r6, lr}

	mrc	p15, 0, r4, c13, c0, 0	@ PID

	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID

	mrc	p15, 0, r6, c2, c0, 0	@ TTB address

	mrc	p15, 0, r7, c1, c0, 0	@ Control register

	stmia	r0, {r4 - r7}

	ldmfd	sp!, {r4 - r7, pc}

	mrc	p15, 0, r6, c1, c0, 0	@ Control register

	stmia	r0, {r4 - r6}

	ldmfd	sp!, {r4 - r6, pc}

ENDPROC(cpu_arm920_do_suspend)



ENTRY(cpu_arm920_do_resume)

	mov	ip, #0

	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs

	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches

	ldmia	r0, {r4 - r7}

	ldmia	r0, {r4 - r6}

	mcr	p15, 0, r4, c13, c0, 0	@ PID

	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID

	mcr	p15, 0, r6, c2, c0, 0	@ TTB address

	mov	r0, r7			@ control register

	mcr	p15, 0, r1, c2, c0, 0	@ TTB address

	mov	r0, r6			@ control register

	b	cpu_resume_mmu

ENDPROC(cpu_arm920_do_resume)

#endif

arch/arm/mm/proc-arm926.S

+8 −9
Original line number Diff line number Diff line
@@ -394,27 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext) 


/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */

.globl	cpu_arm926_suspend_size

.equ	cpu_arm926_suspend_size, 4 * 4

.equ	cpu_arm926_suspend_size, 4 * 3

#ifdef CONFIG_PM_SLEEP

ENTRY(cpu_arm926_do_suspend)

	stmfd	sp!, {r4 - r7, lr}

	stmfd	sp!, {r4 - r6, lr}

	mrc	p15, 0, r4, c13, c0, 0	@ PID

	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID

	mrc	p15, 0, r6, c2, c0, 0	@ TTB address

	mrc	p15, 0, r7, c1, c0, 0	@ Control register

	stmia	r0, {r4 - r7}

	ldmfd	sp!, {r4 - r7, pc}

	mrc	p15, 0, r6, c1, c0, 0	@ Control register

	stmia	r0, {r4 - r6}

	ldmfd	sp!, {r4 - r6, pc}

ENDPROC(cpu_arm926_do_suspend)



ENTRY(cpu_arm926_do_resume)

	mov	ip, #0

	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs

	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches

	ldmia	r0, {r4 - r7}

	ldmia	r0, {r4 - r6}

	mcr	p15, 0, r4, c13, c0, 0	@ PID

	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID

	mcr	p15, 0, r6, c2, c0, 0	@ TTB address

	mov	r0, r7			@ control register

	mcr	p15, 0, r1, c2, c0, 0	@ TTB address

	mov	r0, r6			@ control register

	b	cpu_resume_mmu

ENDPROC(cpu_arm926_do_resume)

#endif

arch/arm/mm/proc-sa1100.S

+10 −11
Original line number Diff line number Diff line
@@ -168,20 +168,19 @@ ENTRY(cpu_sa1100_set_pte_ext) 
	mov	pc, lr



.globl	cpu_sa1100_suspend_size

.equ	cpu_sa1100_suspend_size, 4*4

.equ	cpu_sa1100_suspend_size, 4 * 3

#ifdef CONFIG_PM_SLEEP

ENTRY(cpu_sa1100_do_suspend)

	stmfd	sp!, {r4 - r7, lr}

	stmfd	sp!, {r4 - r6, lr}

	mrc	p15, 0, r4, c3, c0, 0		@ domain ID

	mrc	p15, 0, r5, c2, c0, 0		@ translation table base addr

	mrc	p15, 0, r6, c13, c0, 0		@ PID

	mrc	p15, 0, r7, c1, c0, 0		@ control reg

	stmia	r0, {r4 - r7}			@ store cp regs

	ldmfd	sp!, {r4 - r7, pc}

	mrc	p15, 0, r5, c13, c0, 0		@ PID

	mrc	p15, 0, r6, c1, c0, 0		@ control reg

	stmia	r0, {r4 - r6}			@ store cp regs

	ldmfd	sp!, {r4 - r6, pc}

ENDPROC(cpu_sa1100_do_suspend)



ENTRY(cpu_sa1100_do_resume)

	ldmia	r0, {r4 - r7}			@ load cp regs

	ldmia	r0, {r4 - r6}			@ load cp regs

	mov	ip, #0

	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs

	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache
@@ -189,9 +188,9 @@ ENTRY(cpu_sa1100_do_resume) 
	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB



	mcr	p15, 0, r4, c3, c0, 0		@ domain ID

	mcr	p15, 0, r5, c2, c0, 0		@ translation table base addr

	mcr	p15, 0, r6, c13, c0, 0		@ PID

	mov	r0, r7				@ control register

	mcr	p15, 0, r1, c2, c0, 0		@ translation table base addr

	mcr	p15, 0, r5, c13, c0, 0		@ PID

	mov	r0, r6				@ control register

	b	cpu_resume_mmu

ENDPROC(cpu_sa1100_do_resume)

#endif