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Commit de7ca214 authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
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sh: clock-cpg div4 set_rate() shift fix 



Make sure the div4 bitfield is shifted according
to the enable_bit value in sh_clk_div4_set_rate().

Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 8c563a30

arch/sh/kernel/cpu/clock-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id 
		return idx;



	value = __raw_readl(clk->enable_reg);

	value &= ~0xf;

	value |= idx;

	value &= ~(0xf << clk->enable_bit);

	value |= (idx << clk->enable_bit);

	__raw_writel(value, clk->enable_reg);



	return 0;