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Commit de558cd2 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: adreno a306 support 



As found in apq8016 (used in DragonBoard 410c) and msm8916.

Note that numerically a306 is actually 307 (since a305c already claimed
306).  Nice and confusing.

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 6490ad47

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+9 −3
Original line number Original line Diff line number Diff line
@@ -93,7 +93,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		/* Set up AOOO: */

		/* Set up AOOO: */

		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);



	} else if (adreno_is_a306(adreno_gpu)) {

		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);

		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);

	} else if (adreno_is_a320(adreno_gpu)) {

	} else if (adreno_is_a320(adreno_gpu)) {

		/* Set up 16 deep read/write request queues: */

		/* Set up 16 deep read/write request queues: */

		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);

		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -186,7 +189,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);

	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);





	/* Enable Clock gating: */

	/* Enable Clock gating: */

	if (adreno_is_a320(adreno_gpu))

	if (adreno_is_a306(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);

	else if (adreno_is_a320(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);

	else if (adreno_is_a330v2(adreno_gpu))

	else if (adreno_is_a330v2(adreno_gpu))

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);

		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
@@ -271,7 +276,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);

		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);





	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu)) {

	if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||

			adreno_is_a320(adreno_gpu)) {

		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,

		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |

				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |

drivers/gpu/drm/msm/adreno/adreno_device.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -41,6 +41,14 @@ static const struct adreno_info gpulist[] = { 
		.pfpfw = "a300_pfp.fw",

		.pfpfw = "a300_pfp.fw",

		.gmem  = SZ_256K,

		.gmem  = SZ_256K,

		.init  = a3xx_gpu_init,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(3, 0, 6, 0),

		.revn  = 307,        /* because a305c is revn==306 */

		.name  = "A306",

		.pm4fw = "a300_pm4.fw",

		.pfpfw = "a300_pfp.fw",

		.gmem  = SZ_128K,

		.init  = a3xx_gpu_init,

	}, {

	}, {

		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),

		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),

		.revn  = 320,

		.revn  = 320,

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -197,6 +197,12 @@ static inline bool adreno_is_a305(struct adreno_gpu *gpu) 
	return gpu->revn == 305;

	return gpu->revn == 305;

}

}





static inline bool adreno_is_a306(struct adreno_gpu *gpu)

{

	/* yes, 307, because a305c is 306 */

	return gpu->revn == 307;

}



static inline bool adreno_is_a320(struct adreno_gpu *gpu)

static inline bool adreno_is_a320(struct adreno_gpu *gpu)

{

{

	return gpu->revn == 320;

	return gpu->revn == 320;

drivers/gpu/drm/msm/msm_gpu.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -522,6 +522,7 @@ static irqreturn_t irq_handler(int irq, void *data) 




static const char *clk_names[] = {

static const char *clk_names[] = {

		"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",

		"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",

		"alt_mem_iface_clk",

};

};





int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,

int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,

drivers/gpu/drm/msm/msm_gpu.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -100,7 +100,7 @@ struct msm_gpu { 




	/* Power Control: */

	/* Power Control: */

	struct regulator *gpu_reg, *gpu_cx;

	struct regulator *gpu_reg, *gpu_cx;

	struct clk *ebi1_clk, *grp_clks[5];

	struct clk *ebi1_clk, *grp_clks[6];

	uint32_t fast_rate, slow_rate, bus_freq;

	uint32_t fast_rate, slow_rate, bus_freq;





#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING

#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING