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Commit dd4fe5b2 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Andy Gross
Browse files

firmware: qcom: scm: Expose PAS command 10 as reset-controller 



PAS command 10 is used to assert and deassert the MSS reset via
TrustZone, expose this as a reset-controller to mimic the direct
access case.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent f01e90fe

drivers/firmware/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ config FW_CFG_SYSFS_CMDLINE 
config QCOM_SCM

	bool

	depends on ARM || ARM64

	select RESET_CONTROLLER



config QCOM_SCM_32

	def_bool y

drivers/firmware/qcom_scm-32.c

+13 −0
Original line number Diff line number Diff line
@@ -547,3 +547,16 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) 


	return ret ? : le32_to_cpu(out);

}



int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

{

	__le32 out;

	__le32 in = cpu_to_le32(reset);

	int ret;



	ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET,

			&in, sizeof(in),

			&out, sizeof(out));



	return ret ? : le32_to_cpu(out);

}

drivers/firmware/qcom_scm-64.c

+16 −0
Original line number Diff line number Diff line
@@ -342,3 +342,19 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) 


	return ret ? : res.a1;

}



int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

{

	struct qcom_scm_desc desc = {0};

	struct arm_smccc_res res;

	int ret;



	desc.args[0] = reset;

	desc.args[1] = 0;

	desc.arginfo = QCOM_SCM_ARGS(2);



	ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, &desc,

			    &res);



	return ret ? : res.a1;

}

drivers/firmware/qcom_scm.c

+31 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <linux/of.h>

#include <linux/of_platform.h>

#include <linux/clk.h>

#include <linux/reset-controller.h>



#include "qcom_scm.h"
@@ -29,6 +30,7 @@ struct qcom_scm { 
	struct clk *core_clk;

	struct clk *iface_clk;

	struct clk *bus_clk;

	struct reset_controller_dev reset;

};



static struct qcom_scm *__scm;
@@ -283,6 +285,30 @@ int qcom_scm_pas_shutdown(u32 peripheral) 
}

EXPORT_SYMBOL(qcom_scm_pas_shutdown);



static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,

				     unsigned long idx)

{

	if (idx != 0)

		return -EINVAL;



	return __qcom_scm_pas_mss_reset(__scm->dev, 1);

}



static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,

				       unsigned long idx)

{

	if (idx != 0)

		return -EINVAL;



	return __qcom_scm_pas_mss_reset(__scm->dev, 0);

}



static const struct reset_control_ops qcom_scm_pas_reset_ops = {

	.assert = qcom_scm_pas_reset_assert,

	.deassert = qcom_scm_pas_reset_deassert,

};





static int qcom_scm_probe(struct platform_device *pdev)

{

	struct qcom_scm *scm;
@@ -316,6 +342,11 @@ static int qcom_scm_probe(struct platform_device *pdev) 
		}

	}



	scm->reset.ops = &qcom_scm_pas_reset_ops;

	scm->reset.nr_resets = 1;

	scm->reset.of_node = pdev->dev.of_node;

	reset_controller_register(&scm->reset);



	/* vote for max clk rate for highest performance */

	ret = clk_set_rate(scm->core_clk, INT_MAX);

	if (ret)

drivers/firmware/qcom_scm.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ extern void __qcom_scm_init(void); 
#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD	0x5

#define QCOM_SCM_PAS_SHUTDOWN_CMD	0x6

#define QCOM_SCM_PAS_IS_SUPPORTED_CMD	0x7

#define QCOM_SCM_PAS_MSS_RESET		0xa

extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);

extern int  __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,

		dma_addr_t metadata_phys);
@@ -53,6 +54,7 @@ extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, 
		phys_addr_t addr, phys_addr_t size);

extern int  __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);

extern int  __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);

extern int  __qcom_scm_pas_mss_reset(struct device *dev, bool reset);



/* common error codes */

#define QCOM_SCM_V2_EBUSY	-12