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Commit dd114443 authored by Thor Thayer's avatar Thor Thayer Committed by Mark Brown
Browse files

spi: dw-spi: Convert 16bit accesses to 32bit accesses 



Altera's Arria10 SoC interconnect requires a 32-bit write for APB
peripherals. The current spi-dw driver uses 16-bit accesses in
some locations. This patch converts all the 16-bit reads and
writes to 32-bit reads and writes.

Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]

[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)

Request for test with platforms using the DesignWare SPI IP.

Tested On:
Altera CycloneV development kit
Altera Arria10 development kit
Compile tested for build errors on x86_64 (allyesconfigs)

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Reviewed-and-tested-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 23065096

drivers/spi/spi-dw-mid.c

+5 −5
Original line number Diff line number Diff line
@@ -98,12 +98,12 @@ static void mid_spi_dma_exit(struct dw_spi *dws) 


static irqreturn_t dma_transfer(struct dw_spi *dws)

{

	u16 irq_status = dw_readw(dws, DW_SPI_ISR);

	u16 irq_status = dw_readl(dws, DW_SPI_ISR);



	if (!irq_status)

		return IRQ_NONE;



	dw_readw(dws, DW_SPI_ICR);

	dw_readl(dws, DW_SPI_ICR);

	spi_reset_chip(dws);



	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
@@ -228,14 +228,14 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) 
{

	u16 dma_ctrl = 0;



	dw_writew(dws, DW_SPI_DMARDLR, 0xf);

	dw_writew(dws, DW_SPI_DMATDLR, 0x10);

	dw_writel(dws, DW_SPI_DMARDLR, 0xf);

	dw_writel(dws, DW_SPI_DMATDLR, 0x10);



	if (xfer->tx_buf)

		dma_ctrl |= SPI_DMA_TDMAE;

	if (xfer->rx_buf)

		dma_ctrl |= SPI_DMA_RDMAE;

	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);

	dw_writel(dws, DW_SPI_DMACR, dma_ctrl);



	/* Set the interrupt mask */

	spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);

drivers/spi/spi-dw.c

+12 −12
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ static inline u32 tx_max(struct dw_spi *dws) 
	u32 tx_left, tx_room, rxtx_gap;



	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;

	tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);

	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);



	/*

	 * Another concern is about the tx/rx mismatch, we
@@ -178,7 +178,7 @@ static inline u32 rx_max(struct dw_spi *dws) 
{

	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;



	return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));

	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));

}



static void dw_writer(struct dw_spi *dws)
@@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) 
			else

				txw = *(u16 *)(dws->tx);

		}

		dw_writew(dws, DW_SPI_DR, txw);

		dw_writel(dws, DW_SPI_DR, txw);

		dws->tx += dws->n_bytes;

	}

}
@@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) 
	u16 rxw;



	while (max--) {

		rxw = dw_readw(dws, DW_SPI_DR);

		rxw = dw_readl(dws, DW_SPI_DR);

		/* Care rx only if the transfer's original "rx" is not null */

		if (dws->rx_end - dws->len) {

			if (dws->n_bytes == 1)
@@ -228,11 +228,11 @@ static void int_error_stop(struct dw_spi *dws, const char *msg) 


static irqreturn_t interrupt_transfer(struct dw_spi *dws)

{

	u16 irq_status = dw_readw(dws, DW_SPI_ISR);

	u16 irq_status = dw_readl(dws, DW_SPI_ISR);



	/* Error handling */

	if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {

		dw_readw(dws, DW_SPI_ICR);

		dw_readl(dws, DW_SPI_ICR);

		int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");

		return IRQ_HANDLED;

	}
@@ -257,7 +257,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) 
{

	struct spi_master *master = dev_id;

	struct dw_spi *dws = spi_master_get_devdata(master);

	u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;

	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;



	if (!irq_status)

		return IRQ_NONE;
@@ -354,7 +354,7 @@ static int dw_spi_transfer_one(struct spi_master *master, 
		cr0 |= (chip->tmode << SPI_TMOD_OFFSET);

	}



	dw_writew(dws, DW_SPI_CTRL0, cr0);

	dw_writel(dws, DW_SPI_CTRL0, cr0);



	/* Check if current transfer is a DMA transaction */

	if (master->can_dma && master->can_dma(master, spi, transfer))
@@ -375,7 +375,7 @@ static int dw_spi_transfer_one(struct spi_master *master, 
		}

	} else if (!chip->poll_mode) {

		txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);

		dw_writew(dws, DW_SPI_TXFLTR, txlevel);

		dw_writel(dws, DW_SPI_TXFLTR, txlevel);



		/* Set the interrupt mask */

		imask |= SPI_INT_TXEI | SPI_INT_TXOI |
@@ -499,11 +499,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) 
		u32 fifo;



		for (fifo = 1; fifo < 256; fifo++) {

			dw_writew(dws, DW_SPI_TXFLTR, fifo);

			if (fifo != dw_readw(dws, DW_SPI_TXFLTR))

			dw_writel(dws, DW_SPI_TXFLTR, fifo);

			if (fifo != dw_readl(dws, DW_SPI_TXFLTR))

				break;

		}

		dw_writew(dws, DW_SPI_TXFLTR, 0);

		dw_writel(dws, DW_SPI_TXFLTR, 0);



		dws->fifo_len = (fifo == 1) ? 0 : fifo;

		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);

drivers/spi/spi-dw.h

+0 −10
Original line number Diff line number Diff line
@@ -150,16 +150,6 @@ static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 
	__raw_writel(val, dws->regs + offset);

}



static inline u16 dw_readw(struct dw_spi *dws, u32 offset)

{

	return __raw_readw(dws->regs + offset);

}



static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)

{

	__raw_writew(val, dws->regs + offset);

}



static inline void spi_enable_chip(struct dw_spi *dws, int enable)

{

	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));