Commit dc81081b authored Jun 10, 2009 by Yong Wang Committed by Ingo Molnar Jun 10, 2009

perf_counter/x86: Fix the model number of Intel Core2 processors

Fix the model number of Intel Core2 processors according to the
documentation: Intel Processor Identification with the CPUID
Instruction: http://www.intel.com/support/processors/sb/cs-009861.htm



Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Also-Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <20090610090612.GA26580@ywang-moblin2.bj.intel.com>
[ Added two more model numbers suggested by Arnd Bergmann ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent fecc8ac8

arch/x86/kernel/cpu/perf_counter.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -1407,7 +1407,10 @@ static int intel_pmu_init(void)
		* Install the hw-cache-events table:
		*/
		switch (boot_cpu_data.x86_model) {
		case 17:
		case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
		case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
		case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
		case 29: /* six-core 45 nm xeon "Dunnington" */
		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
		sizeof(hw_cache_event_ids));