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Commit dc3cf93d authored by Yoshifumi Hosoya's avatar Yoshifumi Hosoya Committed by Simon Horman
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ARM: shmobile: r8a7794: Add MMP and VSP1 clocks to device tree 



Signed-off-by: default avatarYoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 3e58a542

arch/arm/boot/dts/r8a7794.dtsi

+9 −5
Original line number Diff line number Diff line
@@ -461,15 +461,19 @@ 
		mstp1_clks: mstp1_clks@e6150134 {

			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;

			clocks = <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,

				 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;

			clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,

				 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,

				 <&zs_clk>, <&zs_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_TMU3

				R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0

				R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1

				R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0

				R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0

				R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S

			>;

			clock-output-names =

				"tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0";

				"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",

				"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";

		};

		mstp2_clks: mstp2_clks@e6150138 {

			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

include/dt-bindings/clock/r8a7794-clock.h

+6 −0
Original line number Diff line number Diff line
@@ -26,12 +26,18 @@ 
#define R8A7794_CLK_MSIOF0		0



/* MSTP1 */

#define R8A7794_CLK_VCP0		1

#define R8A7794_CLK_VPC0		3

#define R8A7794_CLK_TMU1		11

#define R8A7794_CLK_3DG			12

#define R8A7794_CLK_2DDMAC		15

#define R8A7794_CLK_FDP1_0		19

#define R8A7794_CLK_TMU3		21

#define R8A7794_CLK_TMU2		22

#define R8A7794_CLK_CMT0		24

#define R8A7794_CLK_TMU0		25

#define R8A7794_CLK_VSP1_DU0		28

#define R8A7794_CLK_VSP1_S		31



/* MSTP2 */

#define R8A7794_CLK_SCIFA2		2