ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks (dc3cad82) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/mach-shmobile/clock-sh7372.c

+10 −84

Original line number	Original line	Diff line number	Diff line
	@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
	};		};

	/* FSI DIV */		/* FSI DIV */
	static unsigned long fsidiv_recalc(struct clk *clk)		enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
	{
	unsigned long value;

	value = __raw_readl(clk->mapping->base);

	value >>= 16;
	if (value < 2)
	return 0;

	return clk->parent->rate / value;
	}

	static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
	{
	return clk_rate_div_range_round(clk, 2, 0xffff, rate);
	}

	static void fsidiv_disable(struct clk *clk)
	{
	__raw_writel(0, clk->mapping->base);
	}

	static int fsidiv_enable(struct clk *clk)
	{
	unsigned long value;

	value = __raw_readl(clk->mapping->base) >> 16;
	if (value < 2)
	return -EIO;

	__raw_writel((value << 16) \| 0x3, clk->mapping->base);

	return 0;
	}

	static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
	{
	int idx;

	idx = (clk->parent->rate / rate) & 0xffff;
	if (idx < 2)
	return -EINVAL;

	__raw_writel(idx << 16, clk->mapping->base);
	return 0;
	}

	static struct sh_clk_ops fsidiv_clk_ops = {
	.recalc = fsidiv_recalc,
	.round_rate = fsidiv_round_rate,
	.set_rate = fsidiv_set_rate,
	.enable = fsidiv_enable,
	.disable = fsidiv_disable,
	};

	static struct clk_mapping fsidiva_clk_mapping = {
	.phys = FSIDIVA,
	.len = 8,
	};

	static struct clk fsidiva_clk = {
	.ops = &fsidiv_clk_ops,
	.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
	.mapping = &fsidiva_clk_mapping,
	};

	static struct clk_mapping fsidivb_clk_mapping = {		static struct clk fsidivs[] = {
	.phys = FSIDIVB,		[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
	.len = 8,		[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
	};

	static struct clk fsidivb_clk = {
	.ops = &fsidiv_clk_ops,
	.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
	.mapping = &fsidivb_clk_mapping,
	};

	static struct clk *late_main_clks[] = {
	&fsidiva_clk,
	&fsidivb_clk,
	};		};

	enum { MSTP001, MSTP000,		enum { MSTP001, MSTP000,
	@@ -583,8 +507,8 @@ static struct clk_lookup lookups[] = {
	CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),		CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
	CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),		CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
	CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),		CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
	CLKDEV_CON_ID("fsidiva", &fsidiva_clk),		CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
	CLKDEV_CON_ID("fsidivb", &fsidivb_clk),		CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),

	/* DIV4 clocks */		/* DIV4 clocks */
	CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),		CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
	@@ -680,6 +604,8 @@ static struct clk_lookup lookups[] = {
	CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),		CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
	CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),		CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
	CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),		CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
			CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
			CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
	};		};

	void __init sh7372_clock_init(void)		void __init sh7372_clock_init(void)
	@@ -708,8 +634,8 @@ void __init sh7372_clock_init(void)
	if (!ret)		if (!ret)
	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)		if (!ret)
	ret = clk_register(late_main_clks[k]);		ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));		clkdev_add_table(lookups, ARRAY_SIZE(lookups));