Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dba538ff authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86/intel-mid changes from Ingo Molnar:
 "Update the 'intel mid' (mobile internet device) platform code as Intel
  is rolling out more SoC designs.

  This gets rid of most of the 'MRST' platform code in the process,
  mostly by renaming and shuffling code around into their respective
  'intel-mid' platform drivers"

* 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, intel-mid: Do not re-introduce usage of obsolete __cpuinit
  intel_mid: Move platform device setups to their own platform_<device>.* files
  x86: intel-mid: Add section for sfi device table
  intel-mid: sfi: Allow struct devs_id.get_platform_data to be NULL
  intel_mid: Moved SFI related code to sfi.c
  intel_mid: Added custom handler for ipc devices
  intel_mid: Added custom device_handler support
  intel_mid: Refactored sfi_parse_devs() function
  intel_mid: Renamed *mrst* to *intel_mid*
  pci: intel_mid: Return true/false in function returning bool
  intel_mid: Renamed *mrst* to *intel_mid*
  mrst: Fixed indentation issues
  mrst: Fixed printk/pr_* related issues
parents 2dc1733f aeeca404

Documentation/kernel-parameters.txt

+3 −3
Original line number Diff line number Diff line
@@ -3492,11 +3492,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			default x2apic cluster mode on platforms

			supporting x2apic.



	x86_mrst_timer= [X86-32,APBT]

			Choose timer option for x86 Moorestown MID platform.

	x86_intel_mid_timer= [X86-32,APBT]

			Choose timer option for x86 Intel MID platform.

			Two valid options are apbt timer only and lapic timer

			plus one apbt timer for broadcast timer.

			x86_mrst_timer=apbt_only | lapic_and_apbt

			x86_intel_mid_timer=apbt_only | lapic_and_apbt



	xen_emul_unplug=		[HW,X86,XEN]

			Unplug Xen emulated devices

arch/x86/include/asm/mrst.h→arch/x86/include/asm/intel-mid.h

+113 −0
Original line number Diff line number Diff line 
/*

 * mrst.h: Intel Moorestown platform specific setup code

 * intel-mid.h: Intel MID specific setup code

 *

 * (C) Copyright 2009 Intel Corporation

 *
@@ -8,16 +8,39 @@ 
 * as published by the Free Software Foundation; version 2

 * of the License.

 */

#ifndef _ASM_X86_MRST_H

#define _ASM_X86_MRST_H

#ifndef _ASM_X86_INTEL_MID_H

#define _ASM_X86_INTEL_MID_H



#include <linux/sfi.h>

#include <linux/platform_device.h>



extern int pci_mrst_init(void);

extern int intel_mid_pci_init(void);

extern int get_gpio_by_name(const char *name);

extern void intel_scu_device_register(struct platform_device *pdev);

extern int __init sfi_parse_mrtc(struct sfi_table_header *table);

extern int __init sfi_parse_mtmr(struct sfi_table_header *table);

extern int sfi_mrtc_num;

extern struct sfi_rtc_table_entry sfi_mrtc_array[];



/*

 * Here defines the array of devices platform data that IAFW would export

 * through SFI "DEVS" table, we use name and type to match the device and

 * its platform data.

 */

struct devs_id {

	char name[SFI_NAME_LEN + 1];

	u8 type;

	u8 delay;

	void *(*get_platform_data)(void *info);

	/* Custom handler for devices */

	void (*device_handler)(struct sfi_device_table_entry *pentry,

				struct devs_id *dev);

};



#define sfi_device(i)   \

	static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \

	__attribute__((__section__(".x86_intel_mid_dev.init"))) = &i



/*

 * Medfield is the follow-up of Moorestown, it combines two chip solution into

 * one. Other than that it also added always-on and constant tsc and lapic
@@ -25,33 +48,39 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[]; 
 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be

 * identified via MSRs.

 */

enum mrst_cpu_type {

enum intel_mid_cpu_type {

	/* 1 was Moorestown */

	MRST_CPU_CHIP_PENWELL = 2,

	INTEL_MID_CPU_CHIP_PENWELL = 2,

};



extern enum mrst_cpu_type __mrst_cpu_chip;

extern enum intel_mid_cpu_type __intel_mid_cpu_chip;



#ifdef CONFIG_X86_INTEL_MID



static inline enum mrst_cpu_type mrst_identify_cpu(void)

static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)

{

	return __mrst_cpu_chip;

	return __intel_mid_cpu_chip;

}



static inline bool intel_mid_has_msic(void)

{

	return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);

}



#else /* !CONFIG_X86_INTEL_MID */



#define mrst_identify_cpu()    (0)

#define intel_mid_identify_cpu()    (0)

#define intel_mid_has_msic()    (0)



#endif /* !CONFIG_X86_INTEL_MID */



enum mrst_timer_options {

	MRST_TIMER_DEFAULT,

	MRST_TIMER_APBT_ONLY,

	MRST_TIMER_LAPIC_APBT,

enum intel_mid_timer_options {

	INTEL_MID_TIMER_DEFAULT,

	INTEL_MID_TIMER_APBT_ONLY,

	INTEL_MID_TIMER_LAPIC_APBT,

};



extern enum mrst_timer_options mrst_timer_options;

extern enum intel_mid_timer_options intel_mid_timer_options;



/*

 * Penwell uses spread spectrum clock, so the freq number is not exactly
@@ -76,6 +105,9 @@ extern void intel_scu_devices_destroy(void); 
#define MRST_VRTC_MAP_SZ	(1024)

/*#define MRST_VRTC_PGOFFSET	(0xc00) */



extern void mrst_rtc_init(void);

extern void intel_mid_rtc_init(void);



/* the offset for the mapping of global gpio pin to irq */

#define INTEL_MID_IRQ_OFFSET 0x100



#endif /* _ASM_X86_MRST_H */
 
#endif /* _ASM_X86_INTEL_MID_H */

arch/x86/include/asm/mrst-vrtc.h→arch/x86/include/asm/intel_mid_vrtc.h

+2 −2
Original line number Diff line number Diff line 
#ifndef _MRST_VRTC_H

#define _MRST_VRTC_H

#ifndef _INTEL_MID_VRTC_H

#define _INTEL_MID_VRTC_H



extern unsigned char vrtc_cmos_read(unsigned char reg);

extern void vrtc_cmos_write(unsigned char val, unsigned char reg);

arch/x86/include/asm/setup.h

+2 −2
Original line number Diff line number Diff line
@@ -51,9 +51,9 @@ extern void i386_reserve_resources(void); 
extern void setup_default_timer_irq(void);



#ifdef CONFIG_X86_INTEL_MID

extern void x86_mrst_early_setup(void);

extern void x86_intel_mid_early_setup(void);

#else

static inline void x86_mrst_early_setup(void) { }

static inline void x86_intel_mid_early_setup(void) { }

#endif



#ifdef CONFIG_X86_INTEL_CE

arch/x86/include/uapi/asm/bootparam.h

+1 −1
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ enum { 
	X86_SUBARCH_PC = 0,

	X86_SUBARCH_LGUEST,

	X86_SUBARCH_XEN,

	X86_SUBARCH_MRST,

	X86_SUBARCH_INTEL_MID,

	X86_SUBARCH_CE4100,

	X86_NR_SUBARCHS,

};