Merge branch 'cxgb4-next' (db3397b9) · Commits · e / devices / android_kernel_teracube_2e

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

+20 −1

Original line number	Original line	Diff line number	Diff line
	@@ -224,7 +224,6 @@ struct sge_params {
	};		};

	struct tp_params {		struct tp_params {
	unsigned int ntxchan; /* # of Tx channels */
	unsigned int tre; /* log2 of core clocks per TP tick */		unsigned int tre; /* log2 of core clocks per TP tick */
	unsigned int la_mask; /* what events are recorded by TP LA */		unsigned int la_mask; /* what events are recorded by TP LA */
	unsigned short tx_modq_map; /* TX modulation scheduler queue to */		unsigned short tx_modq_map; /* TX modulation scheduler queue to */
	@@ -273,6 +272,7 @@ struct pci_params {

	#define CHELSIO_T4 0x4		#define CHELSIO_T4 0x4
	#define CHELSIO_T5 0x5		#define CHELSIO_T5 0x5
			#define CHELSIO_T6 0x6

	enum chip_type {		enum chip_type {
	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),		T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
	@@ -284,6 +284,10 @@ enum chip_type {
	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),		T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	T5_FIRST_REV = T5_A0,		T5_FIRST_REV = T5_A0,
	T5_LAST_REV = T5_A1,		T5_LAST_REV = T5_A1,

			T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
			T6_FIRST_REV = T6_A0,
			T6_LAST_REV = T6_A0,
	};		};

	struct devlog_params {		struct devlog_params {
	@@ -292,6 +296,15 @@ struct devlog_params {
	u32 size; /* size of log */		u32 size; /* size of log */
	};		};

			/* Stores chip specific parameters */
			struct arch_specific_params {
			u8 nchan;
			u16 mps_rplc_size;
			u16 vfcount;
			u32 sge_fl_db;
			u16 mps_tcam_size;
			};

	struct adapter_params {		struct adapter_params {
	struct sge_params sge;		struct sge_params sge;
	struct tp_params tp;		struct tp_params tp;
	@@ -317,6 +330,7 @@ struct adapter_params {
	unsigned char nports; /* # of ethernet ports */		unsigned char nports; /* # of ethernet ports */
	unsigned char portvec;		unsigned char portvec;
	enum chip_type chip; /* chip code */		enum chip_type chip; /* chip code */
			struct arch_specific_params arch; /* chip specific params */
	unsigned char offload;		unsigned char offload;

	unsigned char bypass;		unsigned char bypass;
	@@ -850,6 +864,11 @@ enum {
	VLAN_REWRITE		VLAN_REWRITE
	};		};

			static inline int is_t6(enum chip_type chip)
			{
			return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
			}

	static inline int is_t5(enum chip_type chip)		static inline int is_t5(enum chip_type chip)
	{		{
	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;		return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c

+135 −45

Original line number	Original line	Diff line number	Diff line
	@@ -1084,41 +1084,89 @@ static inline void tcamxy2valmask(u64 x, u64 y, u8 addr, u64 mask)

	static int mps_tcam_show(struct seq_file seq, void v)		static int mps_tcam_show(struct seq_file seq, void v)
	{		{
	if (v == SEQ_START_TOKEN)		struct adapter *adap = seq->private;
	seq_puts(seq, "Idx Ethernet address Mask Vld Ports PF"		unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
	" VF Replication "
			if (v == SEQ_START_TOKEN) {
			if (adap->params.arch.mps_rplc_size > 128)
			seq_puts(seq, "Idx Ethernet address Mask "
			"Vld Ports PF VF "
			"Replication "
	" P0 P1 P2 P3 ML\n");		" P0 P1 P2 P3 ML\n");
	else {		else
			seq_puts(seq, "Idx Ethernet address Mask "
			"Vld Ports PF VF Replication"
			" P0 P1 P2 P3 ML\n");
			} else {
	u64 mask;		u64 mask;
	u8 addr[ETH_ALEN];		u8 addr[ETH_ALEN];
	struct adapter *adap = seq->private;		bool replicate;
	unsigned int idx = (uintptr_t)v - 2;		unsigned int idx = (uintptr_t)v - 2;
	u64 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));		u64 tcamy, tcamx, val;
	u64 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));		u32 cls_lo, cls_hi, ctl;
	u32 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));		u32 rplc[8] = {0};
	u32 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
	u32 rplc[4] = {0, 0, 0, 0};		if (chip_ver > CHELSIO_T5) {
			/* CtlCmdType - 0: Read, 1: Write
			* CtlTcamSel - 0: TCAM0, 1: TCAM1
			* CtlXYBitSel- 0: Y bit, 1: X bit
			*/

			/* Read tcamy */
			ctl = CTLCMDTYPE_V(0) \| CTLXYBITSEL_V(0);
			if (idx < 256)
			ctl \|= CTLTCAMINDEX_V(idx) \| CTLTCAMSEL_V(0);
			else
			ctl \|= CTLTCAMINDEX_V(idx - 256) \|
			CTLTCAMSEL_V(1);
			t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
			val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
			tcamy = DMACH_G(val) << 32;
			tcamy \|= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);

			/* Read tcamx. Change the control param */
			ctl \|= CTLXYBITSEL_V(1);
			t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
			val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
			tcamx = DMACH_G(val) << 32;
			tcamx \|= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
			} else {
			tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
			tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
			}

			cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
			cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));

	if (tcamx & tcamy) {		if (tcamx & tcamy) {
	seq_printf(seq, "%3u -\n", idx);		seq_printf(seq, "%3u -\n", idx);
	goto out;		goto out;
	}		}

	if (cls_lo & REPLICATE_F) {		rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0;
			if (chip_ver > CHELSIO_T5)
			replicate = (cls_lo & T6_REPLICATE_F);
			else
			replicate = (cls_lo & REPLICATE_F);

			if (replicate) {
	struct fw_ldst_cmd ldst_cmd;		struct fw_ldst_cmd ldst_cmd;
	int ret;		int ret;
			struct fw_ldst_mps_rplc mps_rplc;
			u32 ldst_addrspc;

	memset(&ldst_cmd, 0, sizeof(ldst_cmd));		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
			ldst_addrspc =
			FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS);
	ldst_cmd.op_to_addrspace =		ldst_cmd.op_to_addrspace =
	htonl(FW_CMD_OP_V(FW_LDST_CMD) \|		htonl(FW_CMD_OP_V(FW_LDST_CMD) \|
	FW_CMD_REQUEST_F \|		FW_CMD_REQUEST_F \|
	FW_CMD_READ_F \|		FW_CMD_READ_F \|
	FW_LDST_CMD_ADDRSPACE_V(		ldst_addrspc);
	FW_LDST_ADDRSPC_MPS));
	ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));		ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
	ldst_cmd.u.mps.fid_ctl =		ldst_cmd.u.mps.rplc.fid_idx =
	htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) \|		htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) \|
	FW_LDST_CMD_CTL_V(idx));		FW_LDST_CMD_IDX_V(idx));
	ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,
	sizeof(ldst_cmd), &ldst_cmd);		sizeof(ldst_cmd), &ldst_cmd);
	if (ret)		if (ret)
	@@ -1126,26 +1174,65 @@ static int mps_tcam_show(struct seq_file seq, void v)
	"replication map for idx %d: %d\n",		"replication map for idx %d: %d\n",
	idx, -ret);		idx, -ret);
	else {		else {
	rplc[0] = ntohl(ldst_cmd.u.mps.rplc31_0);		mps_rplc = ldst_cmd.u.mps.rplc;
	rplc[1] = ntohl(ldst_cmd.u.mps.rplc63_32);		rplc[0] = ntohl(mps_rplc.rplc31_0);
	rplc[2] = ntohl(ldst_cmd.u.mps.rplc95_64);		rplc[1] = ntohl(mps_rplc.rplc63_32);
	rplc[3] = ntohl(ldst_cmd.u.mps.rplc127_96);		rplc[2] = ntohl(mps_rplc.rplc95_64);
			rplc[3] = ntohl(mps_rplc.rplc127_96);
			if (adap->params.arch.mps_rplc_size > 128) {
			rplc[4] = ntohl(mps_rplc.rplc159_128);
			rplc[5] = ntohl(mps_rplc.rplc191_160);
			rplc[6] = ntohl(mps_rplc.rplc223_192);
			rplc[7] = ntohl(mps_rplc.rplc255_224);
			}
	}		}
	}		}

	tcamxy2valmask(tcamx, tcamy, addr, &mask);		tcamxy2valmask(tcamx, tcamy, addr, &mask);
	seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x %012llx"		if (chip_ver > CHELSIO_T5)
	"%3c %#x%4u%4d",		seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
	idx, addr[0], addr[1], addr[2], addr[3], addr[4],		"%012llx%3c %#x%4u%4d",
	addr[5], (unsigned long long)mask,		idx, addr[0], addr[1], addr[2], addr[3],
	(cls_lo & SRAM_VLD_F) ? 'Y' : 'N', PORTMAP_G(cls_hi),		addr[4], addr[5], (unsigned long long)mask,
			(cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N',
			PORTMAP_G(cls_hi),
			T6_PF_G(cls_lo),
			(cls_lo & T6_VF_VALID_F) ?
			T6_VF_G(cls_lo) : -1);
			else
			seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
			"%012llx%3c %#x%4u%4d",
			idx, addr[0], addr[1], addr[2], addr[3],
			addr[4], addr[5], (unsigned long long)mask,
			(cls_lo & SRAM_VLD_F) ? 'Y' : 'N',
			PORTMAP_G(cls_hi),
	PF_G(cls_lo),		PF_G(cls_lo),
	(cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);		(cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);
	if (cls_lo & REPLICATE_F)
			if (replicate) {
			if (adap->params.arch.mps_rplc_size > 128)
			seq_printf(seq, " %08x %08x %08x %08x "
			"%08x %08x %08x %08x",
			rplc[7], rplc[6], rplc[5], rplc[4],
			rplc[3], rplc[2], rplc[1], rplc[0]);
			else
	seq_printf(seq, " %08x %08x %08x %08x",		seq_printf(seq, " %08x %08x %08x %08x",
	rplc[3], rplc[2], rplc[1], rplc[0]);		rplc[3], rplc[2], rplc[1], rplc[0]);
			} else {
			if (adap->params.arch.mps_rplc_size > 128)
			seq_printf(seq, "%72c", ' ');
	else		else
	seq_printf(seq, "%36c", ' ');		seq_printf(seq, "%36c", ' ');
			}

			if (chip_ver > CHELSIO_T5)
			seq_printf(seq, "%4u%3u%3u%3u %#x\n",
			T6_SRAM_PRIO0_G(cls_lo),
			T6_SRAM_PRIO1_G(cls_lo),
			T6_SRAM_PRIO2_G(cls_lo),
			T6_SRAM_PRIO3_G(cls_lo),
			(cls_lo >> T6_MULTILISTEN0_S) & 0xf);
			else
	seq_printf(seq, "%4u%3u%3u%3u %#x\n",		seq_printf(seq, "%4u%3u%3u%3u %#x\n",
	SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),		SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
	SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),		SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
	@@ -1416,6 +1503,9 @@ static int rss_config_show(struct seq_file seq, void v)
	seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));		seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)		if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
	seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));		seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
			else
			seq_printf(seq, " VfWrAddr: %3d\n",
			T6_VFWRADDR_G(rssconf));
	seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]);		seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]);
	seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F));		seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F));
	seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F));		seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F));
	@@ -1634,14 +1724,14 @@ static int rss_vf_config_open(struct inode inode, struct file file)
	struct adapter *adapter = inode->i_private;		struct adapter *adapter = inode->i_private;
	struct seq_tab *p;		struct seq_tab *p;
	struct rss_vf_conf *vfconf;		struct rss_vf_conf *vfconf;
	int vf;		int vf, vfcount = adapter->params.arch.vfcount;

	p = seq_open_tab(file, 128, sizeof(*vfconf), 1, rss_vf_config_show);		p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
	if (!p)		if (!p)
	return -ENOMEM;		return -ENOMEM;

	vfconf = (struct rss_vf_conf *)p->data;		vfconf = (struct rss_vf_conf *)p->data;
	for (vf = 0; vf < 128; vf++) {		for (vf = 0; vf < vfcount; vf++) {
	t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,		t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
	&vfconf[vf].rss_vf_vfh);		&vfconf[vf].rss_vf_vfh);
	}		}
	@@ -2033,7 +2123,7 @@ void add_debugfs_files(struct adapter *adap,
	int t4_setup_debugfs(struct adapter *adap)		int t4_setup_debugfs(struct adapter *adap)
	{		{
	int i;		int i;
	u32 size;		u32 size = 0;
	struct dentry *de;		struct dentry *de;

	static struct t4_debugfs_entry t4_debugfs_files[] = {		static struct t4_debugfs_entry t4_debugfs_files[] = {
	@@ -2104,12 +2194,7 @@ int t4_setup_debugfs(struct adapter *adap)
	size = t4_read_reg(adap, MA_EDRAM1_BAR_A);		size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
	add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));		add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
	}		}
	if (is_t4(adap->params.chip)) {		if (is_t5(adap->params.chip)) {
	size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
	if (i & EXT_MEM_ENABLE_F)
	add_debugfs_mem(adap, "mc", MEM_MC,
	EXT_MEM_SIZE_G(size));
	} else {
	if (i & EXT_MEM0_ENABLE_F) {		if (i & EXT_MEM0_ENABLE_F) {
	size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);		size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
	add_debugfs_mem(adap, "mc0", MEM_MC0,		add_debugfs_mem(adap, "mc0", MEM_MC0,
	@@ -2120,6 +2205,11 @@ int t4_setup_debugfs(struct adapter *adap)
	add_debugfs_mem(adap, "mc1", MEM_MC1,		add_debugfs_mem(adap, "mc1", MEM_MC1,
	EXT_MEM1_SIZE_G(size));		EXT_MEM1_SIZE_G(size));
	}		}
			} else {
			if (i & EXT_MEM_ENABLE_F)
			size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
			add_debugfs_mem(adap, "mc", MEM_MC,
			EXT_MEM_SIZE_G(size));
	}		}

	de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,		de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+37 −10

Original line number	Original line	Diff line number	Diff line
	@@ -135,8 +135,10 @@ struct filter_entry {

	#define FW4_FNAME "cxgb4/t4fw.bin"		#define FW4_FNAME "cxgb4/t4fw.bin"
	#define FW5_FNAME "cxgb4/t5fw.bin"		#define FW5_FNAME "cxgb4/t5fw.bin"
			#define FW6_FNAME "cxgb4/t6fw.bin"
	#define FW4_CFNAME "cxgb4/t4-config.txt"		#define FW4_CFNAME "cxgb4/t4-config.txt"
	#define FW5_CFNAME "cxgb4/t5-config.txt"		#define FW5_CFNAME "cxgb4/t5-config.txt"
			#define FW6_CFNAME "cxgb4/t6-config.txt"
	#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"		#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
	#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"		#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
	#define PHY_AQ1202_DEVICEID 0x4409		#define PHY_AQ1202_DEVICEID 0x4409
	@@ -1721,7 +1723,7 @@ static int tid_init(struct tid_info *t)
	bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);		bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
	/* Reserve stid 0 for T4/T5 adapters */		/* Reserve stid 0 for T4/T5 adapters */
	if (!t->stid_base &&		if (!t->stid_base &&
	(is_t4(adap->params.chip) \|\| is_t5(adap->params.chip)))		(CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
	__set_bit(0, t->stid_bmap);		__set_bit(0, t->stid_bmap);

	return 0;		return 0;
	@@ -2108,10 +2110,7 @@ int cxgb4_read_tpte(struct net_device dev, u32 stag, __be32 tpte)
	if (offset < mc0_end) {		if (offset < mc0_end) {
	memtype = MEM_MC0;		memtype = MEM_MC0;
	memaddr = offset - edc1_end;		memaddr = offset - edc1_end;
	} else if (is_t4(adap->params.chip)) {		} else if (is_t5(adap->params.chip)) {
	/* T4 only has a single memory channel */
	goto err;
	} else {
	size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);		size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
	mc1_size = EXT_MEM1_SIZE_G(size) << 20;		mc1_size = EXT_MEM1_SIZE_G(size) << 20;
	mc1_end = mc0_end + mc1_size;		mc1_end = mc0_end + mc1_size;
	@@ -2122,6 +2121,9 @@ int cxgb4_read_tpte(struct net_device dev, u32 stag, __be32 tpte)
	/* offset beyond the end of any memory */		/* offset beyond the end of any memory */
	goto err;		goto err;
	}		}
			} else {
			/* T4/T6 only has a single memory channel */
			goto err;
	}		}
	}		}

	@@ -2286,9 +2288,13 @@ static void process_db_full(struct work_struct *work)
	drain_db_fifo(adap, dbfifo_drain_delay);		drain_db_fifo(adap, dbfifo_drain_delay);
	enable_dbs(adap);		enable_dbs(adap);
	notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);		notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
			if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
	t4_set_reg_field(adap, SGE_INT_ENABLE3_A,		t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
	DBFIFO_HP_INT_F \| DBFIFO_LP_INT_F,		DBFIFO_HP_INT_F \| DBFIFO_LP_INT_F,
	DBFIFO_HP_INT_F \| DBFIFO_LP_INT_F);		DBFIFO_HP_INT_F \| DBFIFO_LP_INT_F);
			else
			t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
			DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
	}		}

	static void sync_txq_pidx(struct adapter adap, struct sge_txq q)		static void sync_txq_pidx(struct adapter adap, struct sge_txq q)
	@@ -2350,7 +2356,7 @@ static void process_db_drop(struct work_struct *work)
	drain_db_fifo(adap, dbfifo_drain_delay);		drain_db_fifo(adap, dbfifo_drain_delay);
	enable_dbs(adap);		enable_dbs(adap);
	notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);		notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
	} else {		} else if (is_t5(adap->params.chip)) {
	u32 dropped_db = t4_read_reg(adap, 0x010ac);		u32 dropped_db = t4_read_reg(adap, 0x010ac);
	u16 qid = (dropped_db >> 15) & 0x1ffff;		u16 qid = (dropped_db >> 15) & 0x1ffff;
	u16 pidx_inc = dropped_db & 0x1fff;		u16 pidx_inc = dropped_db & 0x1fff;
	@@ -2371,6 +2377,7 @@ static void process_db_drop(struct work_struct *work)
	t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);		t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
	}		}

			if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
	t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);		t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
	}		}

	@@ -3390,6 +3397,9 @@ static int adap_init0_config(struct adapter *adapter, int reset)
	case CHELSIO_T5:		case CHELSIO_T5:
	fw_config_file = FW5_CFNAME;		fw_config_file = FW5_CFNAME;
	break;		break;
			case CHELSIO_T6:
			fw_config_file = FW6_CFNAME;
			break;
	default:		default:
	dev_err(adapter->pdev_dev, "Device %d is not supported\n",		dev_err(adapter->pdev_dev, "Device %d is not supported\n",
	adapter->pdev->device);		adapter->pdev->device);
	@@ -3586,7 +3596,24 @@ static struct fw_info fw_info_array[] = {
	.intfver_iscsi = FW_INTFVER(T5, ISCSI),		.intfver_iscsi = FW_INTFVER(T5, ISCSI),
	.intfver_fcoe = FW_INTFVER(T5, FCOE),		.intfver_fcoe = FW_INTFVER(T5, FCOE),
	},		},
			}, {
			.chip = CHELSIO_T6,
			.fs_name = FW6_CFNAME,
			.fw_mod_name = FW6_FNAME,
			.fw_hdr = {
			.chip = FW_HDR_CHIP_T6,
			.fw_ver = __cpu_to_be32(FW_VERSION(T6)),
			.intfver_nic = FW_INTFVER(T6, NIC),
			.intfver_vnic = FW_INTFVER(T6, VNIC),
			.intfver_ofld = FW_INTFVER(T6, OFLD),
			.intfver_ri = FW_INTFVER(T6, RI),
			.intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
			.intfver_iscsi = FW_INTFVER(T6, ISCSI),
			.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
			.intfver_fcoe = FW_INTFVER(T6, FCOE),
			},
	}		}

	};		};

	static struct fw_info *find_fw_info(int chip)		static struct fw_info *find_fw_info(int chip)

drivers/net/ethernet/chelsio/cxgb4/sge.c

+31 −16

Original line number	Original line	Diff line number	Diff line
	@@ -522,14 +522,13 @@ static void unmap_rx_buf(struct adapter adap, struct sge_fl q)

	static inline void ring_fl_db(struct adapter adap, struct sge_fl q)		static inline void ring_fl_db(struct adapter adap, struct sge_fl q)
	{		{
	u32 val;
	if (q->pend_cred >= 8) {		if (q->pend_cred >= 8) {
			u32 val = adap->params.arch.sge_fl_db;

	if (is_t4(adap->params.chip))		if (is_t4(adap->params.chip))
	val = PIDX_V(q->pend_cred / 8);		val \|= PIDX_V(q->pend_cred / 8);
	else		else
	val = PIDX_T5_V(q->pend_cred / 8) \|		val \|= PIDX_T5_V(q->pend_cred / 8);
	DBTYPE_F;
	val \|= DBPRIO_F;

	/* Make sure all memory writes to the Free List queue are		/* Make sure all memory writes to the Free List queue are
	* committed before we tell the hardware about them.		* committed before we tell the hardware about them.
	@@ -1034,7 +1033,7 @@ static void inline_tx_skb(const struct sk_buff skb, const struct sge_txq q,
	* Figure out what HW csum a packet wants and return the appropriate control		* Figure out what HW csum a packet wants and return the appropriate control
	* bits.		* bits.
	*/		*/
	static u64 hwcsum(const struct sk_buff *skb)		static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
	{		{
	int csum_type;		int csum_type;
	const struct iphdr *iph = ip_hdr(skb);		const struct iphdr *iph = ip_hdr(skb);
	@@ -1065,11 +1064,16 @@ static u64 hwcsum(const struct sk_buff *skb)
	goto nocsum;		goto nocsum;
	}		}

	if (likely(csum_type >= TX_CSUM_TCPIP))		if (likely(csum_type >= TX_CSUM_TCPIP)) {
	return TXPKT_CSUM_TYPE_V(csum_type) \|		u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
	TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)) \|		int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
	TXPKT_ETHHDR_LEN_V(skb_network_offset(skb) - ETH_HLEN);
	else {		if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
			hdr_len \|= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
			else
			hdr_len \|= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
			return TXPKT_CSUM_TYPE_V(csum_type) \| hdr_len;
			} else {
	int start = skb_transport_offset(skb);		int start = skb_transport_offset(skb);

	return TXPKT_CSUM_TYPE_V(csum_type) \|		return TXPKT_CSUM_TYPE_V(csum_type) \|
	@@ -1237,9 +1241,15 @@ out_free: dev_kfree_skb_any(skb);
	else		else
	lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len));		lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len));
	cpl = (void *)(lso + 1);		cpl = (void *)(lso + 1);
	cntrl = TXPKT_CSUM_TYPE_V(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) \|
	TXPKT_IPHDR_LEN_V(l3hdr_len) \|		if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
	TXPKT_ETHHDR_LEN_V(eth_xtra_len);		cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
			else
			cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);

			cntrl \|= TXPKT_CSUM_TYPE_V(v6 ?
			TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) \|
			TXPKT_IPHDR_LEN_V(l3hdr_len);
	q->tso++;		q->tso++;
	q->tx_cso += ssi->gso_segs;		q->tx_cso += ssi->gso_segs;
	} else {		} else {
	@@ -1248,7 +1258,8 @@ out_free: dev_kfree_skb_any(skb);
	FW_WR_IMMDLEN_V(len));		FW_WR_IMMDLEN_V(len));
	cpl = (void *)(wr + 1);		cpl = (void *)(wr + 1);
	if (skb->ip_summed == CHECKSUM_PARTIAL) {		if (skb->ip_summed == CHECKSUM_PARTIAL) {
	cntrl = hwcsum(skb) \| TXPKT_IPCSUM_DIS_F;		cntrl = hwcsum(adap->params.chip, skb) \|
			TXPKT_IPCSUM_DIS_F;
	q->tx_cso++;		q->tx_cso++;
	}		}
	}		}
	@@ -2440,6 +2451,8 @@ int t4_sge_alloc_rxq(struct adapter adap, struct sge_rspq iq, bool fwevtq,
	c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);		c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);

	if (fl) {		if (fl) {
			enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);

	/* Allocate the ring for the hardware free list (with space		/* Allocate the ring for the hardware free list (with space
	* for its status page) along with the associated software		* for its status page) along with the associated software
	* descriptor ring. The free list size needs to be a multiple		* descriptor ring. The free list size needs to be a multiple
	@@ -2468,7 +2481,9 @@ int t4_sge_alloc_rxq(struct adapter adap, struct sge_rspq iq, bool fwevtq,
	FW_IQ_CMD_FL0CONGEN_F);		FW_IQ_CMD_FL0CONGEN_F);
	c.fl0dcaen_to_fl0cidxfthresh =		c.fl0dcaen_to_fl0cidxfthresh =
	htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) \|		htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) \|
	FW_IQ_CMD_FL0FBMAX_V(FETCHBURSTMAX_512B_X));		FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
			FETCHBURSTMAX_512B_X :
			FETCHBURSTMAX_256B_X));
	c.fl0size = htons(flsz);		c.fl0size = htons(flsz);
	c.fl0addr = cpu_to_be64(fl->addr);		c.fl0addr = cpu_to_be64(fl->addr);
	}		}

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+506 −56

File changed.

Preview size limit exceeded, changes collapsed.